24#ifndef __YASIMAVR_AVR_USART_H__
25#define __YASIMAVR_AVR_USART_H__
96 virtual void reset(
int flags)
override;
118 void update_bitrate();
119 void extract_rx_data();
#define AVR_ARCHAVR_PUBLIC_API
Definition arch_avr_globals.h:46
Definition arch_avr_usart.cpp:59
Definition arch_avr_usart.cpp:37
Implementation of a USART interface for AVR series.
Definition arch_avr_usart.h:88
Definition sim_signal.h:227
Basic AVR device model.
Definition sim_device.h:61
Generic helper to manage a typical Interrupt Flag/Enable in a I/O register.
Definition sim_interrupt.h:324
Abstract class defining a framework for MCU peripherals.
Definition sim_peripheral.h:286
virtual bool init(Device &device)
Definition sim_peripheral.cpp:60
virtual bool ctlreq(ctlreq_id_t req, ctlreq_data_t *data)
Definition sim_peripheral.cpp:79
virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t &data) override
Definition sim_peripheral.cpp:117
virtual uint8_t ioreg_read_handler(reg_addr_t addr, uint8_t value) override
Definition sim_peripheral.cpp:91
virtual void reset(int flags)
Definition sim_peripheral.cpp:72
Representation of a I/O register address, with validity state.
Definition sim_types.h:60
Definition sim_types.h:431
Represents a field in a I/O register with address.
Definition sim_types.h:348
int ctlreq_id_t
Definition sim_peripheral.h:111
#define YASIMAVR_BEGIN_NAMESPACE
Definition sim_globals.h:58
#define YASIMAVR_END_NAMESPACE
Definition sim_globals.h:59
short int_vect_t
Definition sim_types.h:43
Configuration structure for ArchAVR_USART.
Definition arch_avr_usart.h:39
regbit_t rb_clock_mode
Definition arch_avr_usart.h:60
int_vect_t iv_txe
TXE (DRE) interrupt vector.
Definition arch_avr_usart.h:66
regbit_t rb_tx_enable
TX enable bit.
Definition arch_avr_usart.h:45
regbit_t rb_parity
Definition arch_avr_usart.h:61
regbit_t rb_rxc_inten
RXC interrupt enable bit.
Definition arch_avr_usart.h:46
regbit_compound_t rbc_baud
bitrate register (1 or 2 bytes)
Definition arch_avr_usart.h:54
regbit_compound_t rbc_tx_data
Definition arch_avr_usart.h:42
int_vect_t iv_rxc
RXC interrupt vector.
Definition arch_avr_usart.h:64
regbit_t rb_txc_flag
TXC flag bit.
Definition arch_avr_usart.h:49
regbit_compound_t rbc_rx_data
Data register address.
Definition arch_avr_usart.h:41
regbit_t rb_txe_inten
TXE (DRE) interrupt enable bit.
Definition arch_avr_usart.h:50
regbit_t rb_rx_enable
RX enable bit.
Definition arch_avr_usart.h:44
regbit_t rb_txe_flag
TXE flag bit.
Definition arch_avr_usart.h:51
regbit_t rb_baud_2x
double bitrate bit
Definition arch_avr_usart.h:53
regbit_t rb_perr
Definition arch_avr_usart.h:58
regbit_t rb_stopbits
Definition arch_avr_usart.h:62
regbit_t rb_txc_inten
TXC interrupt enable bit.
Definition arch_avr_usart.h:48
regbit_t rb_ferr
Definition arch_avr_usart.h:56
regbit_t rb_rxc_flag
RXC flag bit.
Definition arch_avr_usart.h:47
int_vect_t iv_txc
TXC interrupt vector.
Definition arch_avr_usart.h:65
regbit_t rb_overrun
Definition arch_avr_usart.h:57
regbit_compound_t rbc_chsize
Definition arch_avr_usart.h:59
Definition sim_peripheral.h:237
Definition sim_ioreg.h:39
Definition sim_signal.h:39