arch_xt_nvm.h Source File

yasimavr: arch_xt_nvm.h Source File
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arch_xt_nvm.h
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1/*
2 * arch_xt_nvm.h
3 *
4 * Copyright 2022-2026 Clement Savergne <csavergne@yahoo.com>
5
6 This file is part of yasim-avr.
7
8 yasim-avr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
12
13 yasim-avr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with yasim-avr. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22//=======================================================================================
23
24#ifndef __YASIMAVR_XT_NVM_H__
25#define __YASIMAVR_XT_NVM_H__
26
27#include "arch_xt_globals.h"
28#include "core/sim_peripheral.h"
29#include "core/sim_interrupt.h"
30#include "core/sim_memory.h"
31
33
34
35//=======================================================================================
36
44
45public:
46
47 explicit ArchXT_USERROW(reg_addr_t base);
48
49 virtual bool init(Device& device) override;
50 virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t& data) override;
51
52private:
53
54 const reg_addr_t m_reg_base;
55 NonVolatileMemory* m_userrow;
56
57};
58
59
60//=======================================================================================
61
70
71public:
72
73 explicit ArchXT_Fuses(reg_addr_t base);
74
75 virtual bool init(Device& device) override;
76 virtual void reset(int flags) override;
77
78private:
79
80 const reg_addr_t m_reg_base;
81 NonVolatileMemory* m_fuses;
82 MemorySectionManager* m_section_manager;
83
84 void configure_flash_sections();
85
86};
87
88
89//=======================================================================================
90
116
128
129public:
130
131 explicit ArchXT_NVM(const ArchXT_NVMConfig& config);
132 virtual ~ArchXT_NVM();
133
134 virtual bool init(Device& device) override;
135 virtual void reset(int flags) override;
136 virtual bool ctlreq(ctlreq_id_t req, ctlreq_data_t* data) override;
137 virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t& data) override;
138
139private:
140
141 enum Command {
142 Cmd_Idle,
143 Cmd_PageWrite,
144 Cmd_PageErase,
145 Cmd_PageEraseWrite,
146 Cmd_BufferErase,
147 Cmd_ChipErase,
148 Cmd_EEPROMErase,
149 };
150
151 enum State {
152 State_Idle,
153 State_Executing,
154 State_Halting,
155 };
156
157 const ArchXT_NVMConfig& m_config;
158 State m_state;
159 uint8_t* m_buffer;
160 uint8_t* m_bufset;
161 int m_mem_index;
162 mem_addr_t m_page;
164
165 InterruptFlag m_ee_intflag;
166
167 MemorySectionManager* m_section_manager;
169 bool m_pending_bootlock;
170
171 NonVolatileMemory* get_memory(int nvm_index);
172 void clear_buffer();
173 void write_nvm(NVM_request_t& nvm_req);
174 void execute_command(Command cmd);
175 unsigned int execute_page_command(Command cmd);
176 void timer_next();
177 void section_raised(const signal_data_t& sigdata, int hooktag);
178
179};
180
181
183
184#endif //__YASIMAVR_XT_NVM_H__
#define AVR_ARCHXT_PUBLIC_API
Definition arch_xt_globals.h:46
Implementation of a fuse NVM peripheral for XT series.
Definition arch_xt_nvm.h:69
Implementation of a NVM controller for Mega0/Mega1 series.
Definition arch_xt_nvm.h:127
Implementation of a User Row peripheral for XT core series.
Definition arch_xt_nvm.h:43
Definition sim_cycle_timer.h:85
Definition sim_signal.h:227
Basic AVR device model.
Definition sim_device.h:61
Generic helper to manage a typical Interrupt Flag/Enable in a I/O register.
Definition sim_interrupt.h:324
Memory section management.
Definition sim_memory.h:124
Non-volatile memory model.
Definition sim_memory.h:42
Abstract class defining a framework for MCU peripherals.
Definition sim_peripheral.h:286
virtual bool init(Device &device)
Definition sim_peripheral.cpp:60
virtual bool ctlreq(ctlreq_id_t req, ctlreq_data_t *data)
Definition sim_peripheral.cpp:79
virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t &data) override
Definition sim_peripheral.cpp:117
virtual void reset(int flags)
Definition sim_peripheral.cpp:72
Representation of a I/O register address, with validity state.
Definition sim_types.h:60
int ctlreq_id_t
Definition sim_peripheral.h:111
#define YASIMAVR_BEGIN_NAMESPACE
Definition sim_globals.h:58
#define YASIMAVR_END_NAMESPACE
Definition sim_globals.h:59
unsigned long mem_addr_t
Definition sim_types.h:41
short int_vect_t
Definition sim_types.h:43
Configuration structure for ArchXT_NVM.
Definition arch_xt_nvm.h:94
reg_addr_t reg_base
Base address for the peripheral I/O registers.
Definition arch_xt_nvm.h:97
int_vect_t iv_eeready
Interrupt vector index for EEREADY.
Definition arch_xt_nvm.h:113
unsigned int buffer_erase_delay
Page buffer erase delay in cycles.
Definition arch_xt_nvm.h:103
mem_addr_t flash_page_size
Page size for the flash.
Definition arch_xt_nvm.h:99
unsigned int page_write_delay
Flash/EEPROM page write operation delay in usecs.
Definition arch_xt_nvm.h:105
unsigned int page_erase_delay
Flash/EEPROM page erase operation delay in usecs.
Definition arch_xt_nvm.h:107
mem_addr_t eeprom_page_size
Page size for the EEPROM.
Definition arch_xt_nvm.h:101
unsigned int eeprom_erase_delay
EEPROM erase operation delay in usecs.
Definition arch_xt_nvm.h:111
unsigned int chip_erase_delay
Chip erase operation delay in usecs.
Definition arch_xt_nvm.h:109
Structure used for AVR_CTLREQ_NVM_REQUEST requests.
Definition sim_peripheral.h:220
Definition sim_peripheral.h:237
Definition sim_ioreg.h:39
Definition sim_signal.h:39