arch_xt_nvm.h Source File
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arch_xt_nvm.h
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Implementation of a User Row peripheral for XT core series.
Definition arch_xt_nvm.h:43
Definition sim_cycle_timer.h:85
Definition sim_signal.h:227
Generic helper to manage a typical Interrupt Flag/Enable in a I/O register.
Definition sim_interrupt.h:324
virtual bool ctlreq(ctlreq_id_t req, ctlreq_data_t *data)
Definition sim_peripheral.cpp:79
virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t &data) override
Definition sim_peripheral.cpp:117
reg_addr_t reg_base
Base address for the peripheral I/O registers.
Definition arch_xt_nvm.h:97
int_vect_t iv_eeready
Interrupt vector index for EEREADY.
Definition arch_xt_nvm.h:113
unsigned int buffer_erase_delay
Page buffer erase delay in cycles.
Definition arch_xt_nvm.h:103
mem_addr_t flash_page_size
Page size for the flash.
Definition arch_xt_nvm.h:99
unsigned int page_write_delay
Flash/EEPROM page write operation delay in usecs.
Definition arch_xt_nvm.h:105
unsigned int page_erase_delay
Flash/EEPROM page erase operation delay in usecs.
Definition arch_xt_nvm.h:107
mem_addr_t eeprom_page_size
Page size for the EEPROM.
Definition arch_xt_nvm.h:101
unsigned int eeprom_erase_delay
EEPROM erase operation delay in usecs.
Definition arch_xt_nvm.h:111
unsigned int chip_erase_delay
Chip erase operation delay in usecs.
Definition arch_xt_nvm.h:109
Definition sim_peripheral.h:237
Definition sim_ioreg.h:39
Definition sim_signal.h:39
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