arch_xt_timer_a.h Source File

yasimavr: arch_xt_timer_a.h Source File
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arch_xt_timer_a.h
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1/*
2 * arch_xt_timer_a.h
3 *
4 * Copyright 2021-2026 Clement Savergne <csavergne@yahoo.com>
5
6 This file is part of yasim-avr.
7
8 yasim-avr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
12
13 yasim-avr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with yasim-avr. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22//=======================================================================================
23
24#ifndef __YASIMAVR_XT_TIMER_A_H__
25#define __YASIMAVR_XT_TIMER_A_H__
26
27#include "arch_xt_globals.h"
28#include "core/sim_peripheral.h"
29#include "core/sim_interrupt.h"
31
33
34class ArchXT_TimerB;
35
36
37//=======================================================================================
38
45/*
46 * Definition of CTLREQ codes for Timer type A
47 */
48
54#define AVR_CTLREQ_TCA_REGISTER_TCB (AVR_CTLREQ_BASE + 1)
55
57
63#define AVR_CTLREQ_TCA_GET_EVENT_HOOK (AVR_CTLREQ_BASE + 2)
64
65
66//=======================================================================================
67
96
107
108public:
109
110 enum SignalId {
111 Signal_CompareOutput
112 };
113
116 Hook_EventB
117 };
118
119 explicit ArchXT_TimerA(const ArchXT_TimerAConfig& config);
120 virtual ~ArchXT_TimerA();
121
122 //Override of Peripheral callbacks
123 virtual bool init(Device& device) override;
124 virtual void reset(int flags) override;
125 virtual bool ctlreq(ctlreq_id_t req, ctlreq_data_t* data) override;
126 virtual uint8_t ioreg_read_handler(reg_addr_t addr, uint8_t value) override;
127 virtual uint8_t ioreg_peek_handler(reg_addr_t addr, uint8_t value) override;
128 virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t& data) override;
129 virtual void sleep(bool on, SleepMode mode) override;
130
131private:
132
133 struct buffered_reg_t {
134 uint16_t value = 0;
135 uint16_t buffer = 0;
136 bool flag = false;
137 };
138
139 enum CounterHookTag {
140 Tag_Single,
141 Tag_SplitLow,
142 Tag_SplitHigh
143 };
144
145 class _PinDriver;
146
147 const ArchXT_TimerAConfig& m_config;
148
149 //***** Counters *****
150 buffered_reg_t m_per;
151 buffered_reg_t m_cmp[ArchXT_TimerAConfig::CompareChannelCount];
152
153 //***** Interrupt and signal management *****
154 InterruptFlag m_ovf_intflag;
155 InterruptFlag m_hunf_intflag;
157
158 DataSignal m_signal;
159
160 //***** Counter management *****
161 bool m_split_mode;
162 PrescaledTimer m_timer;
163 TimerCounter m_sgl_counter; //Main counter in Single mode
164 TimerCounter m_lo_counter; //Low-byte counter in Split mode
165 TimerCounter m_hi_counter; //High-byte counter in Split mode
167
168 uint8_t m_wgmode;
169
170 bool m_EIA_state;
171 bool m_EIB_state;
172 bool m_timer_block;
173
175
176 _PinDriver* m_pin_driver;
177
178 uint8_t read_ioreg_single(reg_addr_t reg_ofs, uint8_t value);
179 uint8_t read_ioreg_split(reg_addr_t reg_ofs, uint8_t value);
180 void write_ioreg_single(reg_addr_t reg_ofs, const ioreg_write_t& data);
181 void write_ioreg_split(reg_addr_t reg_ofs, const ioreg_write_t& data);
182 void update_ALUPD_status();
183 void update_buffered_registers();
184 void set_peripheral_mode(bool split_mode);
185 void update_tick_sources();
186 void configure_single_counter();
187 void update_timer_block(uint8_t ev_ctrl);
188 void set_direction(bool countdown, bool do_reschedule);
189 void set_compare_output(unsigned int index, int change);
190 void update_compare_outputs(int change = 0);
191
192 void counter_raised(const signal_data_t& sigdata, int hooktag);
193 void process_counter_single(const signal_data_t& sigdata);
194 void process_counter_split(const signal_data_t& sigdata, bool low_cnt);
195
196 void event_raised(const signal_data_t& sigdata, int hooktag);
197 void process_EIA(bool event_state);
198 void process_EIB(bool event_state);
199
200 bool execute_command(int cmd, bool cmden);
201
202};
203
204
206
207#endif //__YASIMAVR_XT_TIMER_A_H__
#define AVR_ARCHXT_PUBLIC_API
Definition arch_xt_globals.h:46
Implementation of a Timer/Counter type A for the XT core series.
Definition arch_xt_timer_a.h:106
EventHookTag
Definition arch_xt_timer_a.h:114
@ Hook_EventA
Definition arch_xt_timer_a.h:115
SignalId
Definition arch_xt_timer_a.h:110
Implementation of a Timer/Counter type B for the XT core series.
Definition arch_xt_timer_b.h:66
Definition sim_signal.h:227
Definition sim_signal.h:137
Basic AVR device model.
Definition sim_device.h:61
Generic helper to manage a typical Interrupt Flag/Enable in a I/O register.
Definition sim_interrupt.h:324
Abstract class defining a framework for MCU peripherals.
Definition sim_peripheral.h:286
virtual bool init(Device &device)
Definition sim_peripheral.cpp:60
virtual bool ctlreq(ctlreq_id_t req, ctlreq_data_t *data)
Definition sim_peripheral.cpp:79
virtual void sleep(bool on, SleepMode mode)
Definition sim_peripheral.cpp:125
virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t &data) override
Definition sim_peripheral.cpp:117
virtual uint8_t ioreg_read_handler(reg_addr_t addr, uint8_t value) override
Definition sim_peripheral.cpp:91
virtual uint8_t ioreg_peek_handler(reg_addr_t addr, uint8_t value) override
Definition sim_peripheral.cpp:106
virtual void reset(int flags)
Definition sim_peripheral.cpp:72
Generic model of a Timer with prescaling.
Definition sim_timer.h:63
Generic model of a Counter.
Definition sim_timer.h:164
Representation of a I/O register address, with validity state.
Definition sim_types.h:60
int ctlreq_id_t
Definition sim_peripheral.h:111
#define YASIMAVR_BEGIN_NAMESPACE
Definition sim_globals.h:58
#define YASIMAVR_END_NAMESPACE
Definition sim_globals.h:59
SleepMode
Definition sim_sleep.h:49
short int_vect_t
Definition sim_types.h:43
Configuration structure for ArchXT_TimerA.
Definition arch_xt_timer_a.h:72
Version
Definition arch_xt_timer_a.h:77
@ V2
V1 + Event Input B and RUNSTDBY bit features.
Definition arch_xt_timer_a.h:81
@ V1
Base model version, corresponding to ATMega 0-series implementations.
Definition arch_xt_timer_a.h:79
reg_addr_t reg_base
Base address for the peripheral I/O registers.
Definition arch_xt_timer_a.h:85
Version version
Version of the model.
Definition arch_xt_timer_a.h:93
int_vect_t iv_hunf
Interrupt vector index for TCA_HUNF.
Definition arch_xt_timer_a.h:89
static const int CompareChannelCount
Defines the number of comparison channels supported by the TCA.
Definition arch_xt_timer_a.h:75
int_vect_t ivs_cmp[CompareChannelCount]
Array of vector index for the compare channels interrupts.
Definition arch_xt_timer_a.h:91
int_vect_t iv_ovf
Interrupt vector index for TCA_OVF (a.k.a. TCA_LUNF)
Definition arch_xt_timer_a.h:87
Definition sim_peripheral.h:237
Definition sim_ioreg.h:39
Definition sim_signal.h:39