arch_xt_twi.h Source File

yasimavr: arch_xt_twi.h Source File
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arch_xt_twi.h
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1/*
2 * arch_xt_twi.h
3 *
4 * Copyright 2021-2026 Clement Savergne <csavergne@yahoo.com>
5
6 This file is part of yasim-avr.
7
8 yasim-avr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
12
13 yasim-avr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with yasim-avr. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22//=======================================================================================
23
24#ifndef __YASIMAVR_XT_TWI_H__
25#define __YASIMAVR_XT_TWI_H__
26
27#include "arch_xt_globals.h"
28#include "core/sim_interrupt.h"
29
31
32
33//=======================================================================================
34
51
75
76public:
77
78 ArchXT_TWI(uint8_t num, const ArchXT_TWIConfig& config);
79 virtual ~ArchXT_TWI();
80
81 virtual bool init(Device& device) override;
82 virtual void reset(int flags) override;
83 virtual bool ctlreq(ctlreq_id_t req, ctlreq_data_t* data) override;
84 virtual uint8_t ioreg_read_handler(reg_addr_t addr, uint8_t value) override;
85 virtual uint8_t ioreg_peek_handler(reg_addr_t addr, uint8_t value) override;
86 virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t& data) override;
87
88private:
89
90 class _Client;
91 friend class _Client;
92 class _Host;
93 friend class _Host;
94 class _PinDriver;
95 friend class _PinDriver;
96
97 const ArchXT_TWIConfig& m_config;
98
99 _Client* m_client;
100 _Host* m_host;
101 _PinDriver* m_driver;
104 bool m_pending_host_address;
105 bool m_pending_host_rx_data;
106 bool m_pending_client_rx_data;
107 uint8_t m_host_cmd;
108 uint8_t m_client_cmd;
109
110 InterruptFlag m_intflag_host;
111 InterruptFlag m_intflag_client;
112
113 void reset_host();
114 void clear_host_status();
115 void clear_client_status();
116 bool address_match(uint8_t addr_byte);
117 void execute_host_command();
118 void execute_client_command();
119 void host_signal_raised(const signal_data_t& sigdata, int);
120 void client_signal_raised(const signal_data_t& sigdata, int);
121
122};
123
124
126
127#endif //__YASIMAVR_XT_TWI_H__
#define AVR_ARCHXT_PUBLIC_API
Definition arch_xt_globals.h:46
Definition arch_xt_twi.cpp:105
Definition arch_xt_twi.cpp:85
Definition arch_xt_twi.cpp:54
Implementation of a Two Wire Interface for XT core series.
Definition arch_xt_twi.h:74
Definition sim_signal.h:227
Basic AVR device model.
Definition sim_device.h:61
Generic helper to manage a typical Interrupt Flag/Enable in a I/O register.
Definition sim_interrupt.h:324
Abstract class defining a framework for MCU peripherals.
Definition sim_peripheral.h:286
virtual bool init(Device &device)
Definition sim_peripheral.cpp:60
virtual bool ctlreq(ctlreq_id_t req, ctlreq_data_t *data)
Definition sim_peripheral.cpp:79
virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t &data) override
Definition sim_peripheral.cpp:117
virtual uint8_t ioreg_read_handler(reg_addr_t addr, uint8_t value) override
Definition sim_peripheral.cpp:91
virtual uint8_t ioreg_peek_handler(reg_addr_t addr, uint8_t value) override
Definition sim_peripheral.cpp:106
virtual void reset(int flags)
Definition sim_peripheral.cpp:72
Representation of a I/O register address, with validity state.
Definition sim_types.h:60
int ctlreq_id_t
Definition sim_peripheral.h:111
#define YASIMAVR_BEGIN_NAMESPACE
Definition sim_globals.h:58
#define YASIMAVR_END_NAMESPACE
Definition sim_globals.h:59
short int_vect_t
Definition sim_types.h:43
Configuration structure for ArchXT_TWI.
Definition arch_xt_twi.h:39
int_vect_t iv_client
Interrupt vector index for the client side.
Definition arch_xt_twi.h:46
int_vect_t iv_host
Interrupt vector index for the host side.
Definition arch_xt_twi.h:44
reg_addr_t reg_base
Base address for the peripheral I/O registers.
Definition arch_xt_twi.h:42
bool dual_ctrl
Enable the dual port control.
Definition arch_xt_twi.h:48
Definition sim_peripheral.h:237
Definition sim_ioreg.h:39
Definition sim_signal.h:39