sim_peripheral.h

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/*
 * sim_peripheral.h
 *
 *  Copyright 2022-2026 Clement Savergne <csavergne@yahoo.com>
 
    This file is part of yasim-avr.
 
    yasim-avr is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
 
    yasim-avr is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with yasim-avr.  If not, see <http://www.gnu.org/licenses/>.
 */
 
//=======================================================================================
 
#ifndef __YASIMAVR_PERIPHERAL_H__
#define __YASIMAVR_PERIPHERAL_H__
 
#include "sim_ioreg.h"
#include "sim_signal.h"
#include "sim_logger.h"
 
YASIMAVR_BEGIN_NAMESPACE
 
class Device;
class InterruptHandler;
class CycleTimer;
enum class SleepMode;
 
 
//=======================================================================================
constexpr sim_id_t AVR_IOCTL_CORE     = "CORE";
constexpr sim_id_t AVR_IOCTL_WDT      = "WDT";
constexpr sim_id_t AVR_IOCTL_INTR     = "CPUINT";
constexpr sim_id_t AVR_IOCTL_SLEEP    = "SLPCTRL";
constexpr sim_id_t AVR_IOCTL_CLOCK    = "CLKCTRL";
constexpr sim_id_t AVR_IOCTL_PORT(char c) { return sim_id_t("PORT") + c; }
constexpr sim_id_t AVR_IOCTL_PORTMUX  = "PORTMUX";
constexpr sim_id_t AVR_IOCTL_ADC(char c) { return sim_id_t("ADC") + c; }
constexpr sim_id_t AVR_IOCTL_ACP(char c) { return sim_id_t("ACP") + c; }
constexpr sim_id_t AVR_IOCTL_TIMER(char t, char c) { return (sim_id_t("TC") + t) + c; }
constexpr sim_id_t AVR_IOCTL_EEPROM   = "EEPROM";
constexpr sim_id_t AVR_IOCTL_NVM      = "NVMCTRL";
constexpr sim_id_t AVR_IOCTL_VREF     = "VREF";
constexpr sim_id_t AVR_IOCTL_EXTINT   = "EXTINT";
constexpr sim_id_t AVR_IOCTL_RST      = "RSTCTRL";
constexpr sim_id_t AVR_IOCTL_RTC      = "RTC";
constexpr sim_id_t AVR_IOCTL_UART(char c) { return sim_id_t("USART") + c; }
constexpr sim_id_t AVR_IOCTL_SPI(char c) { return sim_id_t("SPI") + c; }
constexpr sim_id_t AVR_IOCTL_TWI(char c) { return sim_id_t("TWI") + c; }
 
 
//=======================================================================================
 
typedef int ctlreq_id_t;
 
 
#define AVR_CTLREQ_BASE             0x100
 
#define AVR_CTLREQ_GET_SIGNAL       0
 
#define AVR_CTLREQ_CORE_BREAK       (AVR_CTLREQ_BASE + 1)
 
#define AVR_CTLREQ_CORE_SLEEP       (AVR_CTLREQ_BASE + 2)
 
#define AVR_CTLREQ_CORE_WAKEUP      (AVR_CTLREQ_BASE + 3)
 
#define AVR_CTLREQ_CORE_SHORTING    (AVR_CTLREQ_BASE + 4)
 
#define AVR_CTLREQ_CORE_CRASH       (AVR_CTLREQ_BASE + 5)
 
#define AVR_CTLREQ_CORE_RESET       (AVR_CTLREQ_BASE + 6)
 
#define AVR_CTLREQ_CORE_RESET_FLAG  (AVR_CTLREQ_BASE + 7)
 
#define AVR_CTLREQ_CORE_NVM         (AVR_CTLREQ_BASE + 8)
 
#define AVR_CTLREQ_CORE_HALT        (AVR_CTLREQ_BASE + 9)
 
#define AVR_CTLREQ_CORE_SECTIONS    (AVR_CTLREQ_BASE + 10)
 
#define AVR_CTLREQ_WATCHDOG_RESET   (AVR_CTLREQ_BASE + 1)
 
#define AVR_CTLREQ_NVM_REQUEST      (AVR_CTLREQ_BASE + 1)
 
#define AVR_CTLREQ_SLEEP_CALL       (AVR_CTLREQ_BASE + 1)
 
#define AVR_CTLREQ_SLEEP_PSEUDO     (AVR_CTLREQ_BASE + 2)
 
 
 
struct NVM_request_t {
    unsigned char kind;
    int nvm;
    mem_addr_t addr;
    uint16_t data;
    signed char result;
    unsigned short cycles;
};
 
 
struct ctlreq_data_t {
    vardata_t data;
    long long index;
};
 
 
//=======================================================================================
struct base_reg_config_t {
    uint64_t reg_value;
};
 
template<typename T>
int find_reg_config(const std::vector<T>& v, uint64_t reg_value)
{
    for (auto it = v.cbegin(); it != v.cend(); ++it) {
        const base_reg_config_t* cfg = &(*it);
        if (cfg->reg_value == reg_value)
            return it - v.cbegin();
    }
    return -1;
}
 
template<typename T>
const T* find_reg_config_p(const std::vector<T>& v, uint64_t reg_value)
{
    for (const T& cfg : v) {
        if (cfg.reg_value == reg_value)
            return &cfg;
    }
    return nullptr;
}
 
 
 
//=======================================================================================
class AVR_CORE_PUBLIC_API Peripheral: public IORegHandler {
 
public:
 
    explicit Peripheral(ctl_id_t id);
    virtual ~Peripheral();
 
    ctl_id_t id() const;
    std::string name() const;
 
    virtual bool init(Device& device);
 
    virtual void reset(int flags);
 
    virtual bool ctlreq(ctlreq_id_t req, ctlreq_data_t* data);
 
    virtual uint8_t ioreg_read_handler(reg_addr_t addr, uint8_t value) override;
 
    virtual uint8_t ioreg_peek_handler(reg_addr_t addr, uint8_t value) override;
 
    virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t& data) override;
 
    virtual void sleep(bool on, SleepMode mode);
 
    Peripheral(const Peripheral&) = delete;
    Peripheral& operator=(const Peripheral&) = delete;
 
protected:
 
    Device* device() const;
 
    Logger& logger();
 
    void add_ioreg(const regmask_t& rm, IORegister::BitMode bitmode = IORegister::RW);
    void add_ioreg(const regbit_compound_t& rbc, IORegister::BitMode bitmode = IORegister::RW);
    void add_ioreg(reg_addr_t addr, IORegister::BitMode bitmode = IORegister::RW);
    void add_ioreg(reg_addr_t addr, bitmask_t mask, IORegister::BitMode bitmode = IORegister::RW);
 
    uint8_t read_ioreg(const regbit_t& rb) const;
    uint64_t read_ioreg(const regbit_compound_t& rbc) const;
    uint8_t read_ioreg(reg_addr_t addr) const;
    uint8_t read_ioreg(reg_addr_t addr, const bitspec_t& bs) const;
 
    bool test_ioreg(const regbit_t& rb) const;
    bool test_ioreg(const regbit_compound_t& rbc) const;
    bool test_ioreg(reg_addr_t addr, const bitspec_t& bs) const;
    bool test_ioreg(reg_addr_t addr, bitmask_t bm = 0xFF) const;
 
    void write_ioreg(reg_addr_t addr, bitmask_t bm, uint8_t value);
    void write_ioreg(const regbit_t& rb, uint8_t value);
    void write_ioreg(const regbit_compound_t& rbc, uint64_t value);
    void write_ioreg(reg_addr_t addr, uint8_t value);
    void write_ioreg(reg_addr_t addr, const bitspec_t& bs, uint8_t value);
 
    void set_ioreg(reg_addr_t addr, bitmask_t bm = 0xFF);
    void set_ioreg(const regbit_t& rb);
    void set_ioreg(const regbit_compound_t& rbc);
    void set_ioreg(reg_addr_t addr, const bitspec_t& bs);
 
    void clear_ioreg(reg_addr_t addr, bitmask_t bm = 0xFF);
    void clear_ioreg(const regbit_t& rb);
    void clear_ioreg(const regbit_compound_t& rbc);
    void clear_ioreg(reg_addr_t addr, const bitspec_t& bs);
 
    bool register_interrupt(int_vect_t vector, InterruptHandler& handler) const;
 
    Signal* get_signal(ctl_id_t ctl_id) const;
 
private:
 
    ctl_id_t m_id;
    Device* m_device;
    Logger m_logger;
 
};
 
inline ctl_id_t Peripheral::id() const
{
    return m_id;
}
 
inline Device *Peripheral::device() const
{
    return m_device;
}
 
inline Logger& Peripheral::logger()
{
    return m_logger;
}
 
inline void Peripheral::add_ioreg(const regmask_t& rm, IORegister::BitMode bitmode)
{
    add_ioreg(rm.addr, rm.mask, bitmode);
}
 
inline void Peripheral::add_ioreg(reg_addr_t addr, IORegister::BitMode bitmode)
{
    add_ioreg(addr, bitmask_t(0xFF), bitmode);
}
 
inline uint8_t Peripheral::read_ioreg(const regbit_t& rb) const
{
    return rb.extract(read_ioreg(rb.addr));
}
 
inline uint8_t Peripheral::read_ioreg(reg_addr_t addr, const bitspec_t& bs) const
{
    return bs.extract(read_ioreg(addr));
}
 
inline bool Peripheral::test_ioreg(const regbit_t& rb) const
{
    return !!read_ioreg(rb);
}
 
inline bool Peripheral::test_ioreg(const regbit_compound_t& rbc) const
{
    return !!read_ioreg(rbc);
}
 
inline bool Peripheral::test_ioreg(reg_addr_t addr, const bitspec_t& bs) const
{
    return !!read_ioreg(addr, bs);
}
 
inline bool Peripheral::test_ioreg(reg_addr_t addr, bitmask_t bm) const
{
    return !!(bm & read_ioreg(addr));
}
 
inline void Peripheral::write_ioreg(const regbit_t& rb, uint8_t value)
{
    write_ioreg(rb.addr, (bitmask_t) rb, rb.shift_and_mask(value));
}
 
inline void Peripheral::write_ioreg(reg_addr_t addr, uint8_t value)
{
    write_ioreg(addr, bitmask_t(0xFF), value);
}
 
inline void Peripheral::write_ioreg(reg_addr_t addr, const bitspec_t& bs, uint8_t value)
{
    write_ioreg(addr, (bitmask_t) bs, bs.shift_and_mask(value));
}
 
inline void Peripheral::set_ioreg(reg_addr_t addr, bitmask_t bm)
{
    write_ioreg(addr, bm, 0xFF);
}
 
inline void Peripheral::set_ioreg(const regbit_t& rb)
{
    write_ioreg(rb, 0xFF);
}
 
inline void Peripheral::set_ioreg(reg_addr_t addr, const bitspec_t& bs)
{
    write_ioreg(addr, bs, 0xFF);
}
 
inline void Peripheral::clear_ioreg(reg_addr_t addr, bitmask_t bm)
{
    write_ioreg(addr, bm, 0x00);
}
 
inline void Peripheral::clear_ioreg(const regbit_t& rb)
{
    write_ioreg(rb, 0x00);
}
 
inline void Peripheral::clear_ioreg(reg_addr_t addr, const bitspec_t& bs)
{
    write_ioreg(addr, bs, 0x00);
}
 
 
//=======================================================================================
class AVR_CORE_PUBLIC_API DummyController : public Peripheral {
 
public:
 
    struct dummy_register_t {
        regmask_t reg; 
        uint8_t reset; 
    };
 
    DummyController(ctl_id_t id, const std::vector<dummy_register_t>& regs);
 
    virtual bool init(Device& device) override;
    virtual void reset(int flags) override;
 
private:
 
    const std::vector<dummy_register_t> m_registers;
 
};
 
 
YASIMAVR_END_NAMESPACE
 
#endif //__YASIMAVR_PERIPHERAL_H__