Class Port

Inheritance Relationships

class Port : public Peripheral, public SignalHook 

Generic model for a GPIO port controller.

It implements a GPIO port controller for up to 8 pins. The exact number of pins is determined by the device configuration.

At initialization, the port will lookup all possible ports with the letter (e.g. port ‘A’ will lookup and control all pins named ‘PAx’ (x=0 to 7))

CTLREQs supported:

Signals :

Id	Index	Trigger	Data
0	-	Digital state change by any pin	port IN value

Public Functions

explicit Port(char name)

Constructor of the port controller.

Parameters:: name – Upper case letter identifying the port. (eg. ‘A’ denotes port PA)

virtual bool init(Device &device) override

Virtual method called when the device is initialised. This is where the peripheral can allocate its I/O registers, interrupts or connect signals.

virtual void reset() override: Virtual method called when the device is reset. Note that resetting I/O registers is only necessary here if their reset value is not zero.

virtual bool ctlreq(ctlreq_id_t req, ctlreq_data_t *data) override: Virtual method called for a CTL request. The method must return true if the request has been processed.

virtual void raised(const signal_data_t &sigdata, int hooktag) override

Pure virtual callback called during signal raises.

Parameters:

sigdata – Data structure passed on when raising a signal
hooktag – integer passed on when connecting a hook to a signal. For hooks connected to several signals, it provides a mean to identify the caller.

Protected Functions

inline uint8_t pin_mask() const: Returns the pin mask, containing a ‘1’ for each existing pin.

void set_pin_internal_state(uint8_t num, Pin::State state)

Set the pin internal state and raise the signal.