.. _exhale_define_sim__cpu_8cpp_1afa56c66e91ccef4570a1d57864687cf1:

Define get_vd5
==============

- Defined in :ref:`file__home_docs_checkouts_readthedocs.org_user_builds_yasimavr_checkouts_v0.1.5_lib_core_src_core_sim_cpu.cpp`


Define Documentation
--------------------


.. doxygendefine:: get_vd5
   :project: yasimavr