arch_xt_device.h Source File

yasimavr: arch_xt_device.h Source File
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arch_xt_device.h
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1/*
2 * arch_xt_device.h
3 *
4 * Copyright 2021-2025 Clement Savergne <csavergne@yahoo.com>
5
6 This file is part of yasim-avr.
7
8 yasim-avr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
12
13 yasim-avr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with yasim-avr. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22//=======================================================================================
23
24#ifndef __YASIMAVR_XT_DEVICE_H__
25#define __YASIMAVR_XT_DEVICE_H__
26
27#include "arch_xt_globals.h"
28#include "core/sim_core.h"
29#include "core/sim_device.h"
30#include "core/sim_interrupt.h"
31#include "core/sim_types.h"
32
34
35
36//=======================================================================================
37
60
61
62//=======================================================================================
63
68
69
70//=======================================================================================
71
80
81public:
82
84 NVM_EEPROM = NVM_ArchDefined,
85 NVM_USERROW = NVM_ArchDefined + 1,
86 };
87
88 explicit ArchXT_Core(const ArchXT_CoreConfig& variant);
89
90protected:
91
92 virtual uint8_t cpu_read_data(mem_addr_t data_addr) override;
93 virtual void cpu_write_data(mem_addr_t data_addr, uint8_t value) override;
94
95 virtual void dbg_read_data(mem_addr_t start, uint8_t* buf, mem_addr_t len) override;
96 virtual void dbg_write_data(mem_addr_t start, const uint8_t* buf, mem_addr_t len) override;
97
98private:
99
100 NonVolatileMemory m_eeprom;
101 NonVolatileMemory m_userrow;
102
103friend class ArchXT_Device;
104
105};
106
107
108//=======================================================================================
109
114
115public:
116
117 //Definitions for the memory section manager
119 Section_Boot = 0,
122 Section_Count
123 };
124
125 static const size_t SECTION_PAGE_SIZE = 256;
126
127 explicit ArchXT_Device(const ArchXT_DeviceConfig& config);
128 virtual ~ArchXT_Device();
129
130protected:
131
133 virtual bool core_ctlreq(ctlreq_id_t req, ctlreq_data_t* reqdata) override;
134
136 virtual bool program(const Firmware& firmware) override;
137
138private:
139
140 ArchXT_Core m_core_impl;
141 MemorySectionManager m_sections;
142
143};
144
145
147
148#endif //__YASIMAVR_XT_DEVICE_H__
DeviceConfiguration ArchXT_DeviceConfig
Configuration structure for ArchXT_Device.
Definition arch_xt_device.h:67
#define AVR_ARCHXT_PUBLIC_API
Definition arch_xt_globals.h:46
Implementation of a core model for Mega0/Mega1 series.
Definition arch_xt_device.h:79
Implementation of a device model for Mega0/Mega1 series.
Definition arch_xt_device.h:113
FlashSection
Definition arch_xt_device.h:118
@ Section_AppData
Definition arch_xt_device.h:121
@ Section_AppCode
Definition arch_xt_device.h:120
Implementation of a NVM controller for Mega0/Mega1 series.
Definition arch_xt_nvm.h:127
AVR core generic model.
Definition sim_core.h:96
virtual uint8_t cpu_read_data(mem_addr_t data_addr)=0
virtual void cpu_write_data(mem_addr_t data_addr, uint8_t value)=0
@ NVM_ArchDefined
Definition sim_core.h:113
virtual void dbg_read_data(mem_addr_t start, uint8_t *buf, mem_addr_t len)=0
virtual void dbg_write_data(mem_addr_t start, const uint8_t *buf, mem_addr_t len)=0
Basic AVR device model.
Definition sim_device.h:61
Definition sim_firmware.h:53
Memory section management.
Definition sim_memory.h:124
Non-volatile memory model.
Definition sim_memory.h:42
int ctlreq_id_t
Definition sim_peripheral.h:111
#define YASIMAVR_BEGIN_NAMESPACE
Definition sim_globals.h:58
#define YASIMAVR_END_NAMESPACE
Definition sim_globals.h:59
unsigned long mem_addr_t
Definition sim_types.h:41
Configuration structure for ArchXT_Core.
Definition arch_xt_device.h:41
mem_addr_t eepromstart_ds
First address of the EEPROM in the data space.
Definition arch_xt_device.h:52
mem_addr_t flashstart_ds
First address of the flash in the data space.
Definition arch_xt_device.h:47
mem_addr_t flashend_ds
Last address of the flash in the data space.
Definition arch_xt_device.h:49
mem_addr_t userrowsize
Size of the USERROW space.
Definition arch_xt_device.h:57
mem_addr_t eepromsize
Size of the EEPROM.
Definition arch_xt_device.h:44
mem_addr_t eepromend_ds
Last address of the EEPROM in the data space.
Definition arch_xt_device.h:54
Definition sim_config.h:37
Definition sim_config.h:66
Definition sim_peripheral.h:237