Core Class Reference

AVR core generic model. More...

#include <sim_core.h>

Inheritance diagram for Core:

Public Types
enum	NVM {   NVM_Flash , NVM_Fuses , NVM_CommonCount , NVM_ArchDefined = NVM_CommonCount ,   NVM_GetCount = 0xFFFF }

Public Member Functions
	Core (const CoreConfiguration &config)
virtual	~Core ()
const CoreConfiguration &	config () const
bool	init (Device &device)
void	reset ()
int	exec_cycle ()
IORegister *	get_ioreg (reg_addr_t addr)
uint8_t	ioctl_read_ioreg (reg_addr_t addr)
void	ioctl_write_ioreg (reg_addr_t addr, bitmask_t bm, uint8_t value)
void	start_interrupt_inhibit (unsigned int count)
void	set_console_register (reg_addr_t addr)
void	set_direct_LPM_enabled (bool enabled)
	Core (const Core &)=delete
Core &	operator= (const Core &)=delete

Protected Member Functions
uint8_t	cpu_read_ioreg (reg_addr_t addr)
void	cpu_write_ioreg (reg_addr_t addr, uint8_t value)
uint8_t	cpu_read_gpreg (uint8_t reg)
void	cpu_write_gpreg (uint8_t reg, uint8_t value)
virtual uint8_t	cpu_read_data (mem_addr_t data_addr)=0
virtual void	cpu_write_data (mem_addr_t data_addr, uint8_t value)=0
int16_t	cpu_read_flash (flash_addr_t pgm_addr)
bool	use_extended_addressing () const
virtual void	dbg_read_data (mem_addr_t start, uint8_t *buf, mem_addr_t len)=0
virtual void	dbg_write_data (mem_addr_t start, const uint8_t *buf, mem_addr_t len)=0
void	dbg_insert_breakpoint (breakpoint_t &bp)
void	dbg_remove_breakpoint (breakpoint_t &bp)

Static Protected Member Functions
static bool	data_space_map (mem_addr_t addr, mem_addr_t len, mem_addr_t blockstart, mem_addr_t blockend, mem_addr_t *bufofs, mem_addr_t *blockofs, mem_addr_t *result_len)

Protected Attributes
const CoreConfiguration &	m_config
	Reference to the configuration structure, set at construction.
Device *	m_device
	Pointer to the device, set by init()
uint8_t	m_regs [32]
	Array of the 32 general registers.
std::vector< IORegister * >	m_ioregs
	Array of the I/O registers.
uint8_t *	m_sram
	Pointer to the array representing the device RAM memory.
NonVolatileMemory	m_flash
	Non-volatile memory model for the flash.
NonVolatileMemory	m_fuses
	Non-volatile memory model for the fuse bits.
flash_addr_t	m_pc
	Program Counter register, expressed in bytes (unlike the actual device PC)
unsigned int	m_int_inhib_counter
	Counter to inhibit interrupts for a given number of instructions.
DeviceDebugProbe *	m_debug_probe
	Pointer to the generic debug probe.
MemorySectionManager *	m_section_manager

Friends
class	Device
class	DeviceDebugProbe

Detailed Description

AVR core generic model.

Base model for a AVR MCU 8-bits core. This is an abstract class that the different architecture sub-classes must reimplement.

Member Enumeration Documentation

NVM

enum Core::NVM

NVM type enum, used for loading a firmware. The generic core handles only the flash and fuses. The rest (including eeprom) must be handled by the architecture implementations.

Enumerator
NVM_Flash
NVM_Fuses
NVM_CommonCount
NVM_ArchDefined
NVM_GetCount

Constructor & Destructor Documentation

Core() [1/2]

YASIMAVR_USING_NAMESPACE Core::Core ( const CoreConfiguration &  config )

explicit

Build a MCU core.

Parameters

config

Configuration settings for the core

~Core()

Core::~Core ( )

virtual

Destroy a MCU core.

Core() [2/2]

Core::Core ( const Core &  )

delete

Member Function Documentation

config()

const CoreConfiguration & Core::config ( ) const

inline

cpu_read_data()

virtual uint8_t Core::cpu_read_data ( mem_addr_t  data_addr )

protectedpure virtual

Read memory in data address space. This is a pure virtual function that architectures should implement. Implementations should ensure that, if the address is invalid, the behavior should be consistent with the option IgnoreBadCpuIO.

See also

cpu_read_ioreg()

This function is intended for CPU use only.

Parameters

data_addr

Memory address (in 8-bits, data address space) to read

Returns

Content at the flash address

Implemented in ArchAVR_Core, and ArchXT_Core.

cpu_read_flash()

int16_t Core::cpu_read_flash ( flash_addr_t  pgm_addr )

protected

Read the content of the flash non-volatile memory.

This function is intended for CPU use only, to implement the LPM/ELPM instruction.

If the address is out of bounds, the device will crash. If the address is unprogrammed, by default the device will crash but the error can be ignored by setting the option IgnoreBadCpuLPM.

Parameters

pgm_addr

Flash address (in 8-bits, flash address space) to read

Returns

value content at the flash address

cpu_read_gpreg()

uint8_t Core::cpu_read_gpreg ( uint8_t  reg )

protected

Read the content of a general purpose register. This function is intended for CPU model use only.

Parameters

reg	index of the register to read (0-31)

Returns

content of the register

cpu_read_ioreg()

uint8_t Core::cpu_read_ioreg ( reg_addr_t  reg_addr )

protected

Read the content of a I/O register.

If the register does not exist, by default, the device crashes with the code CRASH_BAD_CPU_IO. If the option IgnoreBadCpuIO is set, the error is ignored and the value 0x00 is returned.

This function is intended for CPU model use only.

Parameters

addr	address of the register to access (in IO address space)

Returns

content of the register

cpu_write_data()

virtual void Core::cpu_write_data ( mem_addr_t  data_addr, uint8_t  value  )

protectedpure virtual

Write memory in data address space. This is a pure virtual function that architectures should implement. Implementations should ensure that, if the address is invalid or read-only, the behavior should be consistent with the option IgnoreBadCpuIO.

See also

cpu_write_ioreg()

This function is intended for CPU use only.

Parameters

data_addr	Memory address (in 8-bits, data address space) to read
value	Value to write

Implemented in ArchAVR_Core, and ArchXT_Core.

cpu_write_gpreg()

void Core::cpu_write_gpreg ( uint8_t  reg, uint8_t  value  )

protected

Write the content of a general purpose register. This function is intended for CPU model use only.

Parameters

reg	index of the register to read (0-31)
value	8-bits value to write in the register

cpu_write_ioreg()

void Core::cpu_write_ioreg ( reg_addr_t  reg_addr, uint8_t  value  )

protected

Write the content of a I/O register.

An error will occurred if the register does not exist, or if the call is modifying the read-only part of an existing register. If an error occurred, by default, the device crashes with the code CRASH_BAD_CPU_IO. If the option IgnoreBadCpuIO is set, the error is ignored and the register is unchanged.

This function is intended for CPU model use only.

Parameters

addr	address of the register to access (in IO address space)
value	value to write

data_space_map()

bool Core::data_space_map ( mem_addr_t  data_addr, mem_addr_t  len, mem_addr_t  block_start, mem_addr_t  block_end, mem_addr_t *  buf_ofs, mem_addr_t *  block_ofs, mem_addr_t *  result_len  )

staticprotected

Block memory mapping from data space to a block of memory The block is defined by the interval [blockstart ; blockend] in data space If the data space block defined by (address/len) intersects with the block, the offsets bufofs, blockofs, blocklen are computed and the function returns true

dbg_insert_breakpoint()

void Core::dbg_insert_breakpoint ( breakpoint_t &  bp )

protected

Insert a soft breakpoint at the flash address set in bp This is done by replacing the normal instruction by a BREAK. The normal instruction is backed up in the breakpoint structure.

Parameters

bp	breakpoint to insert

dbg_read_data()

virtual void Core::dbg_read_data ( mem_addr_t  start, uint8_t *  buf, mem_addr_t  len  )

protectedpure virtual

Read memory in data address space. This is a pure virtual function that architectures should implement.

This function is intended for debug probe use only.

Parameters

start	First memory address (in 8-bits, data address space) to read
buf	Buffer where the memory data will be copied into
len	Length of the memory block to read

Implemented in ArchAVR_Core, and ArchXT_Core.

dbg_remove_breakpoint()

void Core::dbg_remove_breakpoint ( breakpoint_t &  bp )

protected

Remove a soft breakpoint at the flash address set in bp This is done by restoring the initial instruction backed up in the breakpoint object.

Parameters

bp	breakpoint to remove

dbg_write_data()

virtual void Core::dbg_write_data ( mem_addr_t  start, const uint8_t *  buf, mem_addr_t  len  )

protectedpure virtual

Write memory in data address space. This is a pure virtual function that architectures should implement.

This function is intended for debug probe use only.

Parameters

start	First memory address (in 8-bits, data address space) to read
buf	Buffer from which the memory data will be copied
len	Length of the memory block to write

Implemented in ArchAVR_Core, and ArchXT_Core.

exec_cycle()

int Core::exec_cycle

(

)

Execute a single instruction cycle with the CPU.

Returns

the number of clock cycle consumed by the instruction, or 0 if something wrong happened.

get_ioreg()

IORegister * Core::get_ioreg

(

reg_addr_t

addr

)

Helper function to get access to IO Registers. If a register does not exist, it is allocated.

Parameters

addr	Address of the register to access (in IO address space)

Returns

IO_Register object

init()

bool Core::init

(

Device &

d

)

Initialise a MCU core.

Returns

the status of initialisation, it's always true.

ioctl_read_ioreg()

uint8_t Core::ioctl_read_ioreg

(

reg_addr_t

reg_addr

)

Read the content of a I/O register.

If the register does not exist, the device crashes with the code CRASH_BAD_CTL_IO.

This function is intended for peripheral model use only.

Parameters

addr	address of the register to access (in IO address space)

Returns

content of the register

ioctl_write_ioreg()

void Core::ioctl_write_ioreg	(	reg_addr_t	addr,
		bitmask_t	mask,
		uint8_t	value
	)

Write the content of a I/O register.

If the register does not exist, the device crashes with the code CRASH_BAD_CTL_IO.

This function is intended for peripheral model use only.

Parameters

rb	regbit of the register/field to access (in IO address space)
value	value to write

operator=()

Core & Core::operator= ( const Core &  )

delete

reset()

void Core::reset

(

)

Reset the core:

• the Program Counter is set to 0x0000,
• all general purpose registers are set to 0x00,
• all I/O registers are set by default to 0x00 (Peripheral models are responsible for resetting registers whose reset values are different),
• the Stack Pointer is set to RAMEND.

set_console_register()

void Core::set_console_register ( reg_addr_t  addr )

inline

set_direct_LPM_enabled()

void Core::set_direct_LPM_enabled ( bool  enabled )

inline

start_interrupt_inhibit()

void Core::start_interrupt_inhibit

(

unsigned int

count

)

Start an interrupt inhibit counter. The counter is decremented for each instruction executed after this call. Raised interrupts will be held up until this counter has dropped to zero.

Parameters

count

initial inhibit counter value

use_extended_addressing()

bool Core::use_extended_addressing ( ) const

inlineprotected

Friends And Related Symbol Documentation

Device

friend class Device

friend

DeviceDebugProbe

friend class DeviceDebugProbe

friend

Member Data Documentation

m_config

const CoreConfiguration& Core::m_config

protected

Reference to the configuration structure, set at construction.

m_debug_probe

DeviceDebugProbe* Core::m_debug_probe

protected

Pointer to the generic debug probe.

m_device

Device* Core::m_device

protected

Pointer to the device, set by init()

m_flash

NonVolatileMemory Core::m_flash

protected

Non-volatile memory model for the flash.

m_fuses

NonVolatileMemory Core::m_fuses

protected

Non-volatile memory model for the fuse bits.

m_int_inhib_counter

unsigned int Core::m_int_inhib_counter

protected

Counter to inhibit interrupts for a given number of instructions.

m_ioregs

std::vector<IORegister*> Core::m_ioregs

protected

Array of the I/O registers.

m_pc

flash_addr_t Core::m_pc

protected

Program Counter register, expressed in bytes (unlike the actual device PC)

m_regs

uint8_t Core::m_regs[32]

protected

Array of the 32 general registers.

m_section_manager

MemorySectionManager* Core::m_section_manager

protected

m_sram

uint8_t* Core::m_sram

protected

Pointer to the array representing the device RAM memory.

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The documentation for this class was generated from the following files:

• sim_core.h
• sim_core.cpp
• sim_cpu.cpp