arch_xt_port.h Source File

yasimavr: arch_xt_port.h Source File
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arch_xt_port.h
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1/*
2 * arch_xt_port.h
3 *
4 * Copyright 2021-2026 Clement Savergne <csavergne@yahoo.com>
5
6 This file is part of yasim-avr.
7
8 yasim-avr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
12
13 yasim-avr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with yasim-avr. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22//=======================================================================================
23
24#ifndef __YASIMAVR_XT_PORT_H__
25#define __YASIMAVR_XT_PORT_H__
26
27#include "arch_xt_globals.h"
28#include "core/sim_interrupt.h"
30
32
33
34//=======================================================================================
48
56
57public:
58
59 ArchXT_Port(char name, const ArchXT_PortConfig& config);
60 virtual ~ArchXT_Port();
61
62 virtual bool init(Device& device) override;
63 virtual uint8_t ioreg_read_handler(reg_addr_t addr, uint8_t value) override;
64 virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t& data) override;
65
66protected:
67
68 virtual void pin_state_changed(uint8_t num, Wire::StateEnum state) override;
69
70private:
71
73
74 const ArchXT_PortConfig& m_config;
75 _InterruptHandler* m_int_handler;
76
77 void update_pin_states();
78 void update_input(uint8_t num);
79
80};
81
82
84
85#endif //__YASIMAVR_XT_PORT_H__
#define AVR_ARCHXT_PUBLIC_API
Definition arch_xt_globals.h:46
Definition arch_xt_port.cpp:49
Implementation of a GPIO port controller for XT core series, based on the generic Port class.
Definition arch_xt_port.h:55
Basic AVR device model.
Definition sim_device.h:61
virtual void ioreg_write_handler(reg_addr_t addr, const ioreg_write_t &data) override
Definition sim_peripheral.cpp:117
virtual uint8_t ioreg_read_handler(reg_addr_t addr, uint8_t value) override
Definition sim_peripheral.cpp:91
Generic model for a GPIO port controller.
Definition sim_port.h:52
virtual bool init(Device &device) override
Definition sim_port.cpp:46
virtual void pin_state_changed(uint8_t num, Wire::StateEnum state)
Definition sim_port.cpp:133
StateEnum
Definition sim_wire.h:63
Representation of a I/O register address, with validity state.
Definition sim_types.h:60
#define YASIMAVR_BEGIN_NAMESPACE
Definition sim_globals.h:58
#define YASIMAVR_END_NAMESPACE
Definition sim_globals.h:59
short int_vect_t
Definition sim_types.h:43
Configuration structure for ArchXT_Port.
Definition arch_xt_port.h:38
int_vect_t iv_port
Interrupt vector index for the port.
Definition arch_xt_port.h:45
reg_addr_t reg_base_vport
Base address for the virtual port I/O registers.
Definition arch_xt_port.h:43
reg_addr_t reg_base_port
Base address for the peripheral I/O registers.
Definition arch_xt_port.h:41
Definition sim_ioreg.h:39