Port Class Reference

yasimavr: Port Class Reference

yasimavr

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Generic model for a GPIO port controller. More...

#include <sim_port.h>

Inheritance diagram for Port:

Public Member Functions
	Port (char name)

virtual bool	init (Device &device) override

virtual void	reset (int flags) override

virtual bool	ctlreq (ctlreq_id_t req, ctlreq_data_t *data) override

Public Member Functions inherited from Peripheral
	Peripheral (ctl_id_t id)

virtual	~Peripheral ()

ctl_id_t	id () const
	Unique identifier of the peripheral.

std::string	name () const
	The name of the peripheral.

virtual uint8_t	ioreg_read_handler (reg_addr_t addr, uint8_t value) override

virtual uint8_t	ioreg_peek_handler (reg_addr_t addr, uint8_t value) override

virtual void	ioreg_write_handler (reg_addr_t addr, const ioreg_write_t &data) override

virtual void	sleep (bool on, SleepMode mode)

	Peripheral (const Peripheral &)=delete

Peripheral &	operator= (const Peripheral &)=delete

Public Member Functions inherited from IORegHandler
virtual	~IORegHandler ()=default

Protected Member Functions
bitmask_t	pin_mask () const
	Returns the pin mask, containing a '1' for each existing pin.

Pin *	pin (uint8_t num) const

void	set_pin_internal_state (uint8_t num, const Pin::controls_t &controls)

virtual void	pin_state_changed (uint8_t num, Wire::StateEnum state)

Protected Member Functions inherited from Peripheral
Device *	device () const
	Access to the device. It is null before init() is called.

Logger &	logger ()
	Logging object associated with this peripheral.

bool	register_interrupt (int_vect_t vector, InterruptHandler &handler) const

Signal *	get_signal (ctl_id_t ctl_id) const

void	add_ioreg (const regmask_t &rm, IORegister::BitMode bitmode=IORegister::RW)

void	add_ioreg (const regbit_compound_t &rbc, IORegister::BitMode bitmode=IORegister::RW)

void	add_ioreg (reg_addr_t addr, IORegister::BitMode bitmode=IORegister::RW)

void	add_ioreg (reg_addr_t addr, bitmask_t mask, IORegister::BitMode bitmode=IORegister::RW)

uint8_t	read_ioreg (const regbit_t &rb) const

uint64_t	read_ioreg (const regbit_compound_t &rbc) const

uint8_t	read_ioreg (reg_addr_t addr) const

uint8_t	read_ioreg (reg_addr_t addr, const bitspec_t &bs) const

bool	test_ioreg (const regbit_t &rb) const

bool	test_ioreg (const regbit_compound_t &rbc) const

bool	test_ioreg (reg_addr_t addr, const bitspec_t &bs) const

bool	test_ioreg (reg_addr_t addr, bitmask_t bm=0xFF) const

void	write_ioreg (reg_addr_t addr, bitmask_t bm, uint8_t value)

void	write_ioreg (const regbit_t &rb, uint8_t value)

void	write_ioreg (const regbit_compound_t &rbc, uint64_t value)

void	write_ioreg (reg_addr_t addr, uint8_t value)

void	write_ioreg (reg_addr_t addr, const bitspec_t &bs, uint8_t value)

void	set_ioreg (reg_addr_t addr, bitmask_t bm=0xFF)

void	set_ioreg (const regbit_t &rb)

void	set_ioreg (const regbit_compound_t &rbc)

void	set_ioreg (reg_addr_t addr, const bitspec_t &bs)

void	clear_ioreg (reg_addr_t addr, bitmask_t bm=0xFF)

void	clear_ioreg (const regbit_t &rb)

void	clear_ioreg (const regbit_compound_t &rbc)

void	clear_ioreg (reg_addr_t addr, const bitspec_t &bs)

Detailed Description

Generic model for a GPIO port controller.

It implements a GPIO port controller for up to 8 pins. The exact number of pins is determined by the device configuration.

At initialisation, the port will lookup all possible ports with the letter (e.g. port 'A' will lookup and control all pins named 'PAx' (x=0 to 7))

CTLREQs supported:

AVR_CTLREQ_GET_SIGNAL

Signals :

Id	Index	Trigger	Data
0	-	Digital state change by any pin	port IN value

Constructor & Destructor Documentation

◆ Port()

YASIMAVR_USING_NAMESPACE Port::Port ( char name )

explicit

Constructor of the port controller.

Parameters

name	Upper case letter identifying the port. (eg. 'A' denotes port PA)

Member Function Documentation

◆ ctlreq()

bool Port::ctlreq	(	ctlreq_id_t	req,
		ctlreq_data_t *	data
	)

overridevirtual

Virtual method called for a CTL request. The method must return true if the request has been processed.

Reimplemented from Peripheral.

◆ init()

bool Port::init ( Device & device )

overridevirtual

Virtual method called when the device is initialised. This is where the peripheral can allocate its I/O registers, interrupts or connect signals.

Returns: boolean indicates the success of all allocations.

Reimplemented from Peripheral.

Reimplemented in ArchAVR_Port, and ArchXT_Port.

◆ pin()

Pin * Port::pin ( uint8_t num ) const

inlineprotected

◆ pin_mask()

bitmask_t Port::pin_mask ( ) const

inlineprotected

Returns the pin mask, containing a '1' for each existing pin.

◆ pin_state_changed()

void Port::pin_state_changed	(	uint8_t	num,
		Wire::StateEnum	state
	)

protectedvirtual

Callback method called when the resolved state of a pin has changed.

See also: set_pin_internal_state

Reimplemented in ArchAVR_Port, and ArchXT_Port.

◆ reset()

void Port::reset ( int flags )

overridevirtual

Virtual method called when the device is reset. Note that resetting I/O registers is only necessary here if their reset value is not zero.

Parameters

flags Reset flags (OR'ed combination of Device::ResetFlag enumeration values)

Reimplemented from Peripheral.

Reimplemented in ArchAVR_Port.

◆ set_pin_internal_state()

void Port::set_pin_internal_state	(	uint8_t	num,
		const Pin::controls_t &	controls
	)

protected

Set the pin internal state and raise the signal.

Parameters

num	index of the pin (0 to 7)
state	new state for the pin

See also: pin_state_changed

The documentation for this class was generated from the following files:

Port Class Reference

Public Member Functions

Protected Member Functions

Detailed Description

Constructor & Destructor Documentation

◆ Port()

Member Function Documentation

◆ ctlreq()

◆ init()

◆ pin()

◆ pin_mask()

◆ pin_state_changed()

◆ reset()

◆ set_pin_internal_state()