sim_cpu.cpp File Reference

yasimavr: sim_cpu.cpp File Reference
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sim_cpu.cpp File Reference
#include "sim_core.h"
#include "sim_debug.h"
#include "sim_device.h"

Macros

#define CPU_READ_GPREG(d)    (m_regs[(d)])
 
#define CPU_WRITE_GPREG(d, v)    (m_regs[(d)] = (v))
 
#define get_flash16le(addr)    (m_flash[addr] | (m_flash[addr + 1] << 8))
 
#define get_d5(o)    const uint8_t d = (o >> 4) & 0x1f;
 
#define get_vd5(o)
 
#define get_r5(o)    const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf);
 
#define get_d5_a6(o)
 
#define get_vd5_s3(o)
 
#define get_vd5_s3_mask(o)
 
#define get_vd5_vr5(o)
 
#define get_d5_vr5(o)
 
#define get_h4_k8(o)
 
#define get_vh4_k8(o)
 
#define get_d5_q6(o)
 
#define get_a5(o)    const uint8_t a = ((o >> 3) & 0x1f);
 
#define get_a5_b3(o)
 
#define get_a5_b3mask(o)
 
#define get_o12(op)    const int16_t o = ((int16_t)((op << 4) & 0xffff)) >> 3;
 
#define get_vp2_k6(o)
 
#define get_sreg_bit(o)    const uint8_t b = (o >> 4) & 7;
 
#define get_r16le(r)    (CPU_READ_GPREG(r) | (CPU_READ_GPREG(r + 1) << 8))
 
#define set_r16le(r, v)
 
#define set_flags_zns(res)
 
#define set_flags_zns16(res)
 
#define set_flags_add_zns(res, rd, rr)
 
#define set_flags_sub_zns(res, rd, rr)
 
#define set_flags_Rzns(res)
 
#define set_flags_sub_Rzns(res, rd, rr)
 
#define set_flags_zcvs(res, vr)
 
#define set_flags_zcnvs(res, vr)
 
#define set_flags_znv0s(res)
 
#define INVALID_OPCODE
 
#define TRACE_JUMP    if (m_debug_probe) m_debug_probe->_cpu_notify_jump(new_pc)
 
#define TRACE_CALL    if (m_debug_probe) m_debug_probe->_cpu_notify_call(new_pc)
 
#define TRACE_RET    if (m_debug_probe) m_debug_probe->_cpu_notify_ret()
 
#define TRACE_OP(f, ...)
 
#define EIND_VALID    (use_extended_addressing() && m_config.eind.valid())
 
#define RAMPZ_VALID    (use_extended_addressing() && m_config.rampz.valid())
 

Functions

const char * sreg_to_str (const uint8_t *sreg, char *sreg_str)
 

Variables

YASIMAVR_USING_NAMESPACE const char sreg_flag_names [8] = {'c', 'z', 'n', 'v', 's', 'h', 't', 'i'}
 

Macro Definition Documentation

◆ CPU_READ_GPREG

#define CPU_READ_GPREG (   d)     (m_regs[(d)])

◆ CPU_WRITE_GPREG

#define CPU_WRITE_GPREG (   d,
  v 
)     (m_regs[(d)] = (v))

◆ EIND_VALID

#define EIND_VALID    (use_extended_addressing() && m_config.eind.valid())

◆ get_a5

#define get_a5 (   o)     const uint8_t a = ((o >> 3) & 0x1f);

◆ get_a5_b3

#define get_a5_b3 (   o)
Value:
get_a5(o) \
const uint8_t b = o & 0x7;
get_a5
#define get_a5(o)
Definition sim_cpu.cpp:106

◆ get_a5_b3mask

#define get_a5_b3mask (   o)
Value:
get_a5(o) \
const uint8_t mask = 1 << (o & 0x7);

◆ get_d5

#define get_d5 (   o)     const uint8_t d = (o >> 4) & 0x1f;

◆ get_d5_a6

#define get_d5_a6 (   o)
Value:
get_d5(o) \
const uint8_t a = ((((o >> 9) & 3) << 4) | ((o) & 0xf));
get_d5
#define get_d5(o)
Definition sim_cpu.cpp:62

◆ get_d5_q6

#define get_d5_q6 (   o)
Value:
get_d5(o) \
const uint8_t q = ((o & 0x2000) >> 8) | ((o & 0x0c00) >> 7) | (o & 0x7);

◆ get_d5_vr5

#define get_d5_vr5 (   o)
Value:
get_d5(o) \
get_r5(o) \
const uint8_t vr = CPU_READ_GPREG(r);
CPU_READ_GPREG
#define CPU_READ_GPREG(d)
Definition sim_cpu.cpp:53

◆ get_flash16le

#define get_flash16le (   addr)     (m_flash[addr] | (m_flash[addr + 1] << 8))

◆ get_h4_k8

#define get_h4_k8 (   o)
Value:
const uint8_t h = 16 + ((o >> 4) & 0xf); \
const uint8_t k = ((o & 0x0f00) >> 4) | (o & 0xf);

◆ get_o12

#define get_o12 (   op)     const int16_t o = ((int16_t)((op << 4) & 0xffff)) >> 3;

◆ get_r16le

#define get_r16le (   r)     (CPU_READ_GPREG(r) | (CPU_READ_GPREG(r + 1) << 8))

◆ get_r5

#define get_r5 (   o)     const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf);

◆ get_sreg_bit

#define get_sreg_bit (   o)     const uint8_t b = (o >> 4) & 7;

◆ get_vd5

#define get_vd5 (   o)
Value:
get_d5(o) \
const uint8_t vd = CPU_READ_GPREG(d);

◆ get_vd5_s3

#define get_vd5_s3 (   o)
Value:
get_vd5(o) \
const uint8_t s = o & 7;
get_vd5
#define get_vd5(o)
Definition sim_cpu.cpp:65

◆ get_vd5_s3_mask

#define get_vd5_s3_mask (   o)
Value:
get_vd5_s3(o) \
const uint8_t mask = 1 << s;
get_vd5_s3
#define get_vd5_s3(o)
Definition sim_cpu.cpp:76

◆ get_vd5_vr5

#define get_vd5_vr5 (   o)
Value:
get_r5(o) \
get_d5(o) \
const uint8_t vd = CPU_READ_GPREG(d), vr = CPU_READ_GPREG(r);
get_r5
#define get_r5(o)
Definition sim_cpu.cpp:69

◆ get_vh4_k8

#define get_vh4_k8 (   o)
Value:
get_h4_k8(o) \
const uint8_t vh = CPU_READ_GPREG(h);
get_h4_k8
#define get_h4_k8(o)
Definition sim_cpu.cpp:94

◆ get_vp2_k6

#define get_vp2_k6 (   o)
Value:
const uint8_t p = 24 + ((o >> 3) & 0x6); \
const uint8_t k = ((o & 0x00c0) >> 2) | (o & 0xf); \
const uint16_t vp = CPU_READ_GPREG(p) | (CPU_READ_GPREG(p + 1) << 8);

◆ INVALID_OPCODE

#define INVALID_OPCODE
Value:
do { \
char msg[50]; \
sprintf(msg, "Bad opcode 0x%04x at PC=0x%04lx", opcode, m_pc); \
m_device->crash(CRASH_INVALID_OPCODE, msg); \
} while(0);
CRASH_INVALID_OPCODE
#define CRASH_INVALID_OPCODE
Definition sim_device.h:49

◆ RAMPZ_VALID

#define RAMPZ_VALID    (use_extended_addressing() && m_config.rampz.valid())

◆ set_flags_add_zns

#define set_flags_add_zns (   res,
  rd,
  rr 
)
Value:
uint8_t add_carry = (rd & rr) | (rr & ~res) | (~res & rd); \
m_sreg[SREG_H] = (add_carry >> 3) & 1; \
m_sreg[SREG_C] = (add_carry >> 7) & 1; \
m_sreg[SREG_V] = (((rd & rr & ~res) | (~rd & ~rr & res)) >> 7) & 1; \
set_flags_zns(res);
SREG_V
@ SREG_V
Definition sim_core.h:54
SREG_H
@ SREG_H
Definition sim_core.h:56
SREG_C
@ SREG_C
Definition sim_core.h:51

◆ set_flags_Rzns

#define set_flags_Rzns (   res)
Value:
if (res) m_sreg[SREG_Z] = 0; \
m_sreg[SREG_N] = (res >> 7) & 1; \
m_sreg[SREG_S] = m_sreg[SREG_N] ^ m_sreg[SREG_V];
SREG_Z
@ SREG_Z
Definition sim_core.h:52
SREG_N
@ SREG_N
Definition sim_core.h:53
SREG_S
@ SREG_S
Definition sim_core.h:55

◆ set_flags_sub_Rzns

#define set_flags_sub_Rzns (   res,
  rd,
  rr 
)
Value:
uint8_t sub_carry = (~rd & rr) | (rr & res) | (res & ~rd); \
m_sreg[SREG_H] = (sub_carry >> 3) & 1; \
m_sreg[SREG_C] = (sub_carry >> 7) & 1; \
m_sreg[SREG_V] = (((rd & ~rr & ~res) | (~rd & rr & res)) >> 7) & 1; \
set_flags_Rzns(res);

◆ set_flags_sub_zns

#define set_flags_sub_zns (   res,
  rd,
  rr 
)
Value:
uint8_t sub_carry = (~rd & rr) | (rr & res) | (res & ~rd); \
m_sreg[SREG_H] = (sub_carry >> 3) & 1; \
m_sreg[SREG_C] = (sub_carry >> 7) & 1; \
m_sreg[SREG_V] = (((rd & ~rr & ~res) | (~rd & rr & res)) >> 7) & 1; \
set_flags_zns(res);

◆ set_flags_zcnvs

#define set_flags_zcnvs (   res,
  vr 
)
Value:
m_sreg[SREG_Z] = res == 0; \
m_sreg[SREG_C] = vr & 1; \
m_sreg[SREG_N] = res >> 7; \
m_sreg[SREG_V] = m_sreg[SREG_N] ^ m_sreg[SREG_C]; \
m_sreg[SREG_S] = m_sreg[SREG_N] ^ m_sreg[SREG_V]; \

◆ set_flags_zcvs

#define set_flags_zcvs (   res,
  vr 
)
Value:
m_sreg[SREG_Z] = res == 0; \
m_sreg[SREG_C] = vr & 1; \
m_sreg[SREG_V] = m_sreg[SREG_N] ^ m_sreg[SREG_C]; \
m_sreg[SREG_S] = m_sreg[SREG_N] ^ m_sreg[SREG_V]; \

◆ set_flags_zns

#define set_flags_zns (   res)
Value:
m_sreg[SREG_Z] = (res == 0); \
m_sreg[SREG_N] = (res >> 7) & 1; \
m_sreg[SREG_S] = m_sreg[SREG_N] ^ m_sreg[SREG_V];

◆ set_flags_zns16

#define set_flags_zns16 (   res)
Value:
m_sreg[SREG_Z] = res == 0; \
m_sreg[SREG_N] = (res >> 15) & 1; \
m_sreg[SREG_S] = m_sreg[SREG_N] ^ m_sreg[SREG_V];

◆ set_flags_znv0s

#define set_flags_znv0s (   res)
Value:
m_sreg[SREG_V] = 0; \
set_flags_zns(res);

◆ set_r16le

#define set_r16le (   r,
  v 
)
Value:
CPU_WRITE_GPREG(r, (v)); \
CPU_WRITE_GPREG(r + 1, (v) >> 8);
CPU_WRITE_GPREG
#define CPU_WRITE_GPREG(d, v)
Definition sim_cpu.cpp:56

◆ TRACE_CALL

#define TRACE_CALL    if (m_debug_probe) m_debug_probe->_cpu_notify_call(new_pc)

◆ TRACE_JUMP

#define TRACE_JUMP    if (m_debug_probe) m_debug_probe->_cpu_notify_jump(new_pc)

◆ TRACE_OP

#define TRACE_OP (   f,
  ... 
)
Value:
m_device->logger().log(Logger::Level_Trace, "PC=0x%04X SREG=%s | " f, \
m_pc, \
sreg_to_str(m_sreg, sreg_str), \
##__VA_ARGS__)
Logger::Level_Trace
@ Level_Trace
Definition sim_logger.h:101
sreg_to_str
const char * sreg_to_str(const uint8_t *sreg, char *sreg_str)
Definition sim_cpu.cpp:42

◆ TRACE_RET

#define TRACE_RET    if (m_debug_probe) m_debug_probe->_cpu_notify_ret()

Function Documentation

◆ sreg_to_str()

const char * sreg_to_str ( const uint8_t *  sreg,
char *  sreg_str 
)

Variable Documentation

◆ sreg_flag_names

YASIMAVR_USING_NAMESPACE const char sreg_flag_names[8] = {'c', 'z', 'n', 'v', 's', 'h', 't', 'i'}
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