Two Wire Interface framework

Namespaces
namespace	TWI
	Common enums and signal definitions for TWI classes.

Classes
class	TWI::EndPoint
	An endpoint connected to a TWI bus. Represents a device connected to a TWI bus model and implements the basic level logic common to a host and a client. More...
class	TWI::Client
	Base abstract definition for a TWI client. This class implements the basic state machine to interface a TWI bus as a client. It is design to be controlled by a upper layer object (a controller). The interface notifies the controller of bus events (start, address, etc) via the signals and the controller shall use the API of this class to react accordingly. More...
class	TWI::Host
	Base abstract definition for a TWI host. This class implements the basic state machine to interface a TWI bus as a host. It is design to be controlled by a upper layer object (a controller). The interface notifies the controller of bus events (start, address, etc) via the signals and the controller shall use the API of this class to react accordingly. More...
struct	ArchAVR_TWIConfig
	Configuration structure for ArchAVR_TWI. More...
class	ArchAVR_TWI
	Implementation of a TWI model for the AVR series. More...
struct	ArchXT_TWIConfig
	Configuration structure for ArchXT_TWI. More...
class	ArchXT_TWI
	Implementation of a Two Wire Interface for XT core series. More...

Controller requests definition for SPI
#define	AVR_CTLREQ_TWI_BUS_ERROR   (AVR_CTLREQ_BASE + 1)

Detailed Description

This code (tentatively) defines a simulation of a TWI (a.k.a. I2C or SMBus) implementation.

It supports multiple hosts/clients, arbitration and bus collision detections. Hoever, it is not multi-thread safe.

It is implemented by 3 classes:

• EndPoint is an abstract interface defining a generic device connected to a TWI bus.
• Client : Basic state machine & transitions for a client side interface.
• Host : Basic state machine & transitions for a host side interface.

These classes are abstract, the way classes access the SCL and SDA line must be defined by reimplementation by overriding set_line_state() and using line_state_changed().

Client and Host are designed to be controlled by an upper level object (a controller). The controller gets notified or events on the bus by signalling, and shall use the interface API to react accordingly.

Macro Definition Documentation

AVR_CTLREQ_TWI_BUS_ERROR

#define AVR_CTLREQ_TWI_BUS_ERROR   (AVR_CTLREQ_BASE + 1)

Request to inject a TWI bus error.

• data->index is 0 for the host side, 1 for the client side.