TWI::Host Class Reference

Base abstract definition for a TWI host. This class implements the basic state machine to interface a TWI bus as a host. It is design to be controlled by a upper layer object (a controller). The interface notifies the controller of bus events (start, address, etc) via the signals and the controller shall use the API of this class to react accordingly. More...

#include <sim_twi.h>

Inheritance diagram for TWI::Host:

Public Types
enum	State {   State_Disabled = 0 , State_Idle , State_Start , State_AddressTx ,   State_AddressAck , State_DataTx , State_DataTxAck , State_DataRx ,   State_DataRxAck , State_Stop , State_BusBusy , State_ArbLost ,   State_Count }

Public Member Functions
	Host ()
void	init (CycleManager &manager)
State	state () const
void	set_enabled (bool enabled)
bool	enabled () const
void	reset ()
void	set_bit_delay (cycle_count_t delay)
bool	bus_busy () const
bool	active () const
bool	clock_hold () const
bool	clock_stretched () const
unsigned char	rw () const
bool	ack () const
bool	start_transfer ()
bool	set_address (uint8_t addr_rw)
bool	start_data_tx (uint8_t data)
bool	start_data_rx ()
bool	set_ack (bool ack)
bool	stop_transfer ()
Signal &	signal ()
virtual cycle_count_t	next (cycle_count_t when) override
	Callback from the cycle loop.
Public Member Functions inherited from TWI::EndPoint
	EndPoint ()
virtual	~EndPoint ()=default
void	line_state_changed (TWI::Line line, bool dig_state)
bool	get_clock_drive () const
bool	get_data_drive () const
Public Member Functions inherited from CycleTimer
	CycleTimer ()
	CycleTimer (const CycleTimer &other)
virtual	~CycleTimer ()
bool	scheduled () const
	Returns true if this timer is scheduled with a manager.
bool	paused () const
cycle_count_t	remaining_delay () const
CycleTimer &	operator= (const CycleTimer &other)

Protected Member Functions
virtual void	clock_level_changed (bool level) override
virtual void	data_level_changed (bool level) override
Protected Member Functions inherited from TWI::EndPoint
virtual void	set_line_state (TWI::Line line, bool dig_state)=0
void	set_clock_drive (bool level)
bool	get_clock_level () const
void	set_data_drive (bool level)
bool	get_data_level () const

Detailed Description

Base abstract definition for a TWI host. This class implements the basic state machine to interface a TWI bus as a host. It is design to be controlled by a upper layer object (a controller). The interface notifies the controller of bus events (start, address, etc) via the signals and the controller shall use the API of this class to react accordingly.

See also

TWI, EndPoint, Client

Member Enumeration Documentation

State

enum TWI::Host::State

Enumerator
State_Disabled	Host disabled
State_Idle	Host idle
State_Start	Sending a START condition.
State_AddressTx	Sending an address/RW byte.
State_AddressAck	Waiting for a ACK/NACK bit after an address/RW byte.
State_DataTx	Sending a data byte.
State_DataTxAck	Waiting for a ACK/NACK bit after sending a data byte.
State_DataRx	Receiving a data byte.
State_DataRxAck	Sending a ACK/NACK bit after receiving a data byte.
State_Stop	Sending a STOP condition.
State_BusBusy	START condition by another host detected on the bus.
State_ArbLost	Arbitration lost.
State_Count	Total number of states.

Constructor & Destructor Documentation

Host()

Host::Host

(

)

Construct a host interface

Member Function Documentation

ack()

bool TWI::Host::ack ( ) const

inline

Returns the latest state of the ACK bit, either sent by this host, or received by a client, after an address or a data byte.

Returns

true for ACK, false for NACK

active()

bool Host::active

(

)

const

Returns whether the host is currently active, i.e. participating in bus traffic. For a host, it means it's currently owning the bus.

bus_busy()

bool Host::bus_busy

(

)

const

Returns whether the bus is currently busy.

clock_hold()

bool TWI::Host::clock_hold ( ) const

inline

Returns whether the host is currently holding the bus clock.

clock_level_changed()

void Host::clock_level_changed ( bool  level )

overrideprotectedvirtual

Implements TWI::EndPoint.

clock_stretched()

bool Host::clock_stretched

(

)

const

Returns whether the clock line is currently stretched by an end point other than this host.

data_level_changed()

void Host::data_level_changed ( bool  level )

overrideprotectedvirtual

Implements TWI::EndPoint.

enabled()

bool TWI::Host::enabled ( ) const

inline

Returns true if the host is enabled, false if disabled.

init()

void Host::init

(

CycleManager &

manager

)

Initialisation of the interface, must be called before any operation.

next()

cycle_count_t Host::next ( cycle_count_t  when )

overridevirtual

Callback from the cycle loop.

Note

there's no guarantee the method will be called exactly on the required 'when' cycle. The only guarantee is "called 'when' <= 'current cycle'", the implementations must account for this.

Parameters

when	current 'when' cycle, at which the timer was scheduled

Returns

the next 'when' the timer requires to be called at.

Note

The next 'when' can be in the 'past' (i.e. <= 'current cycle'). In this case, the timer will be called again within the same cycle with the given next 'when'. The only constraint is that it must be greater than the previous 'when'. If it's negative or zero, the timer is removed from the queue.

Implements CycleTimer.

reset()

void Host::reset

(

)

Reset the interface to the Idle state. No-op if the interface is disabled.

rw()

unsigned char TWI::Host::rw ( ) const

inline

Returns the direction of the current request, depending on the latest RW bit sent.

Returns

1 for a Read Request, 0 for a Write Request

set_ack()

bool Host::set_ack

(

bool

ack

)

Set the ack reply, after a data byte has been received.

Parameters

ack	true for ACK, false for NACK

Returns

true if the call was 'legal' i.e. the interface was waiting for a ACK, false otherwise

set_address()

bool Host::set_address

(

uint8_t

addr_rw

)

Send an address byte on the bus.

Returns

true if the call was 'legal', false otherwise

set_bit_delay()

void Host::set_bit_delay

(

cycle_count_t

delay

)

Set the duration of one bit.

Parameters

delay

bit duration in simulation cycles

set_enabled()

void Host::set_enabled

(

bool

enabled

)

Enable/disable the interface.

signal()

Signal & TWI::Host::signal ( )

inline

Getter for the host signal.

start_data_rx()

bool Host::start_data_rx

(

)

Start receiving a data byte, for a Read Request.

Returns

true if the call was 'legal', false otherwise

start_data_tx()

bool Host::start_data_tx

(

uint8_t

data

)

Start transmitting a data byte, for a Write Request.

Parameters

data	byte to be transmitted

Returns

true if the call was 'legal', false otherwise

start_transfer()

bool Host::start_transfer

(

)

Start a transfer on the bus. A Start or Repeated Start condition will be transmitted.

Returns

true if the call was 'legal', false otherwise

state()

Host::State TWI::Host::state ( ) const

inline

Getter for the state of the host.

stop_transfer()

bool Host::stop_transfer

(

)

End a transfer, a Stop condition will be transmitted.

Returns

true if the call was 'legal', false otherwise

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The documentation for this class was generated from the following files:

• sim_twi.h
• sim_twi.cpp