Class List

Here are the classes, structs, unions and interfaces with brief descriptions:

[detail level 12]

►NACP	Generic Analog Comparator definitions
Cchannel_config_t
►NADC	Generic ADC definitions
Cchannel_config_t
►NSPI	Generic Serial Peripheral Interface definitions
CEndPoint	An endpoint connected to a SPI bus. Represents a device connected to a SPI bus model and acting as a host or client. This is primarily intended to help simulate peripherals connected to the MCU model. Note that this class only implements the logic require to shift bytes across the SPI bus in all modes or bit orders
►NTWI	Common enums and signal definitions for TWI classes
CClient	Base abstract definition for a TWI client. This class implements the basic state machine to interface a TWI bus as a client. It is design to be controlled by a upper layer object (a controller). The interface notifies the controller of bus events (start, address, etc) via the signals and the controller shall use the API of this class to react accordingly
CEndPoint	An endpoint connected to a TWI bus. Represents a device connected to a TWI bus model and implements the basic level logic common to a host and a client
CHost	Base abstract definition for a TWI host. This class implements the basic state machine to interface a TWI bus as a host. It is design to be controlled by a upper layer object (a controller). The interface notifies the controller of bus events (start, address, etc) via the signals and the controller shall use the API of this class to react accordingly
►NUART	Common enums and signal definitions for UART classes
CUSART	Generic model defining an universal synchronous/asynchronous serial interface a.k.a. USART
CAbstractInterruptFlag	Abstract interrupt flag
CAbstractSimLoop	Common base class for simulation loops
CArchAVR_ACP	Implementation of an Analog Comparator for AVR series
►CArchAVR_ACPConfig	Configuration structure for ArchAVR_ACP
Cmux_config_t
CArchAVR_ADC	Implementation of an ADC for AVR series
►CArchAVR_ADCConfig	Configuration structure for ArchAVR_ADC
Creference_config_t
Ctrigger_config_t
CArchAVR_Core	Implementation of a CPU core for AVR series The main addition is to handle the address mapping in data space
CArchAVR_CoreConfig
CArchAVR_Device	Implementation of a MCU for AVR series
CArchAVR_ExtInt	Implementation of a model for a External Interrupts peripheral for AVR series
►CArchAVR_ExtIntConfig	Configuration structure for ArchAVR_ExtInt
Cext_int_t
Cpc_int_t
CArchAVR_Fuses	Implementation of a fuse NVM peripheral for AVR series
►CArchAVR_FusesConfig	Configuration structure for ArchAVR_Fuses
Cbootsize_config_t
CArchAVR_IntCtrl	Implementation of a interrupt controller for AVR series
CArchAVR_IntCtrlConfig
CArchAVR_MiscConfig	Configuration structure for ArchAVR_MiscRegCtrl
CArchAVR_MiscRegCtrl	Implementation of a misc controller for AVR series
►CArchAVR_NVM	Implementation of a NVM controller for AVR series
CEE_Timer
CSPM_Timer
CArchAVR_NVMConfig	Configuration structure for ArchAVR_NVM
CArchAVR_Port	Implementation of a GPIO port controller for AVR series
CArchAVR_PortConfig	Configuration structure for ArchAVR_Port
CArchAVR_ResetCtrl	Implementation of a Reset controller for AVR core series
CArchAVR_ResetCtrlConfig	Configuration structure for ArchAVR_ResetCtrl
►CArchAVR_SPI	Implementation of a SPI interface for AVR series Features:
C_Controller
C_PinDriver
CArchAVR_SPIConfig	Configuration structure for ArchAVR_SPI
►CArchAVR_Timer	Timer/Counter model for AVR series
COutputCompareChannel
►CArchAVR_TimerConfig	Configuration structure for ArchAVR_Timer
Cclock_config_t	Configuration structure for clock source/prescaler options
CCOM_config_t	Configuration structure for one COM setting
Cmode_config_t	Configuration structure for timer modes
COC_config_t	Configuration structure for one compare channel
Cvector_config_t	Configuration structure for one interrupt vector
►CArchAVR_TWI	Implementation of a TWI model for the AVR series
C_Client
C_Host
C_PinDriver
CArchAVR_TWIConfig	Configuration structure for ArchAVR_TWI
►CArchAVR_USART	Implementation of a USART interface for AVR series
C_Controller
C_PinDriver
CArchAVR_USARTConfig	Configuration structure for ArchAVR_USART
►CArchAVR_USI	Implementation of a Universal Serial Interface for AVR series
C_PinDriver
CArchAVR_USIConfig	Configuration structure for ArchAVR_USI
CArchAVR_VREF	Implementation of a Voltage Reference controller for AVR series
CArchAVR_WDT	Implementation of a Watchdog Timer for AVR series
CArchAVR_WDTConfig	Configuration structure for ArchAVR_WDT
CArchXT_ACP	Implementation of an Analog Comparator for XT core series
CArchXT_ACPConfig	Configuration structure for ArchXT_ACP
CArchXT_ADC	Implementation of an ADC for XT series
►CArchXT_ADCConfig	Configuration structure for ArchXT_ADC
Creference_config_t
CArchXT_Core	Implementation of a core model for Mega0/Mega1 series
CArchXT_CoreConfig	Configuration structure for ArchXT_Core
CArchXT_Device	Implementation of a device model for Mega0/Mega1 series
CArchXT_Fuses	Implementation of a fuse NVM peripheral for XT series
►CArchXT_IntCtrl	Implementation of a Interrupt Controller for XT core series
Cvect_info_t
CArchXT_IntCtrlConfig	Configuration structure for ArchXT_IntCtrl
CArchXT_MiscConfig	Configuration structure for ArchXT_MiscRegCtrl
CArchXT_MiscRegCtrl	Implementation of a controller for misc registers for XT core series
CArchXT_NVM	Implementation of a NVM controller for Mega0/Mega1 series
CArchXT_NVMConfig	Configuration structure for ArchXT_NVM
►CArchXT_Port	Implementation of a GPIO port controller for XT core series, based on the generic Port class
C_InterruptHandler
CArchXT_PortConfig	Configuration structure for ArchXT_Port
►CArchXT_PortMuxConfig	Configuration structure for ArchXT_PortMuxCtrl
Cmux_config_t
Cmux_map_entry_t	Structure defining the mux ID corresponding to a register field value
CArchXT_PortMuxCtrl	Implementation of a generic portmux controller for XT core series
CArchXT_ResetCtrl	Implementation of a Reset controller for XT core series
►CArchXT_RTC	Implementation of a RTC controller for XT core series
CTimerHook
►CArchXT_RTCConfig	Configuration structure for ArchXT_RTC
Cclksel_config_t	Configuration structure for each supported source clock
►CArchXT_SPI	Implementation of a Serial Peripheral Interface controller for the XT core series
C_Controller
C_InterruptHandler
C_PinDriver
CArchXT_SPIConfig	Configuration structure for ArchXT_SPI
►CArchXT_TimerA	Implementation of a Timer/Counter type A for the XT core series
C_PinDriver
CArchXT_TimerAConfig	Configuration structure for ArchXT_TimerA
►CArchXT_TimerB	Implementation of a Timer/Counter type B for the XT core series
C_PinDriver
CArchXT_TimerBConfig	Configuration structure for ArchXT_TimerB
►CArchXT_TWI	Implementation of a Two Wire Interface for XT core series
C_Client
C_Host
C_PinDriver
CArchXT_TWIConfig	Configuration structure for ArchXT_TWI
►CArchXT_USART	Implementation of a USART interface for XT core series
C_Controller
C_PinDriver
CArchXT_USARTConfig	Configuration structure for ArchXT_USART
CArchXT_USERROW	Implementation of a User Row peripheral for XT core series
CArchXT_VREF	Implementation of a voltage reference controller for XT core series
►CArchXT_VREFConfig	Configuration structure for ArchXT_VREF
Cchannel_t
Creference_config_t	Structure defining the source of a voltage reference
CArchXT_WDT	Implementation of a Watchdog Timer for XT core series
CArchXT_WDTConfig	Configuration structure for ArchXT_WDT
CAsyncSimLoop	Asynchronous simulation loop It is designed when simulation need to interact with code running in another thread. Examples: debugger, GUI, sockets
Cbase_reg_config_t
Cbitmask_t	Bit mask structure for bitwise operations on 8-bits registers
Cbitspec_t	Bit spec structure. Represent a field in a I/O register. It works the same as bitmask_t except used bits must be consecutive
CBoundFunctionCycleTimer
CBoundFunctionSignalHook
Cbreakpoint_t	Breakpoint structure
CCore	AVR core generic model
CCoreConfiguration
Cctlreq_data_t
►CCycleManager
CTimerSlot
CCycleTimer
CDataSignal
CDataSignalMux
CDevice	Basic AVR device model
CDeviceConfiguration
CDeviceDebugProbe
►CDummyController	Generic dummy peripheral
Cdummy_register_t
►CFirmware
Cblock_view_t
CSymbol
►CInterruptController	Generic interrupt controller
CIRQ_t
CInterruptFlag	Generic helper to manage a typical Interrupt Flag/Enable in a I/O register
CInterruptHandler	Abstract interface to a interrupt controller
Cioreg_write_t
CIORegDispatcher
CIORegHandler
CIORegister
CLogger
CLogHandler
CLogWriter
CMemorySectionManager	Memory section management
CNonVolatileMemory	Non-volatile memory model
CNVM_request_t	Structure used for AVR_CTLREQ_NVM_REQUEST requests
CPeripheral	Abstract class defining a framework for MCU peripherals
►CPin	MCU pin model
Ccontrols_t
CPinDriver	MCU pin driver
►CPinManager	MCU pin manager
Cdrv_entry_t
Cpin_entry_t
CPort	Generic model for a GPIO port controller
CPrescaledTimer	Generic model of a Timer with prescaling
Creg_addr_t	Representation of a I/O register address, with validity state
Cregbit_compound_t
Cregbit_t	Represents a field in a I/O register with address
Cregmask_t	Address + bit mask structure
CSignal	Signalling framework class
Csignal_data_t
CSignalHook
Csim_id_t	Representation of a ID internally represented as a 64-bits integer but can be initialised with a string
CSimLoop	Synchronous simulation loop Basic synchronous simulation loop. It is designed for "fast" simulations with a deterministic set of stimuli. It can run in "fast" mode or "real-time" mode
►CSleepConfig	Configuration structure for a generic sleep mode controller
Cmode_config_t	Configuration structure for each supported sleep mode
CSleepController	Generic sleep mode controller
CTimerCounter	Generic model of a Counter
Cvardata_t
CVREF	Generic model for managing VREF for analog peripherals (ADC, analog comparator)
►CWire	General Purpose wire model
Cstate_t