| ►CAbstractSimLoop | Common base class for simulation loops |
| CAsyncSimLoop | Asynchronous simulation loop It is designed when simulation need to interact with code running in another thread. Examples: debugger, GUI, sockets |
| CSimLoop | Synchronous simulation loop Basic synchronous simulation loop. It is designed for "fast" simulations with a deterministic set of stimuli. It can run in "fast" mode or "real-time" mode |
| CArchAVR_ACPConfig | Configuration structure for ArchAVR_ACP |
| CArchAVR_ADCConfig | Configuration structure for ArchAVR_ADC |
| CArchAVR_ExtIntConfig | Configuration structure for ArchAVR_ExtInt |
| CArchAVR_FusesConfig | Configuration structure for ArchAVR_Fuses |
| CArchAVR_IntCtrlConfig | |
| CArchAVR_MiscConfig | Configuration structure for ArchAVR_MiscRegCtrl |
| CArchAVR_NVMConfig | Configuration structure for ArchAVR_NVM |
| CArchAVR_PortConfig | Configuration structure for ArchAVR_Port |
| CArchAVR_ResetCtrlConfig | Configuration structure for ArchAVR_ResetCtrl |
| CArchAVR_SPIConfig | Configuration structure for ArchAVR_SPI |
| CArchAVR_TimerConfig | Configuration structure for ArchAVR_Timer |
| CArchAVR_TWIConfig | Configuration structure for ArchAVR_TWI |
| CArchAVR_USARTConfig | Configuration structure for ArchAVR_USART |
| CArchAVR_USIConfig | Configuration structure for ArchAVR_USI |
| CArchAVR_WDTConfig | Configuration structure for ArchAVR_WDT |
| CArchXT_ACPConfig | Configuration structure for ArchXT_ACP |
| CArchXT_ADCConfig | Configuration structure for ArchXT_ADC |
| CArchXT_IntCtrlConfig | Configuration structure for ArchXT_IntCtrl |
| CArchXT_MiscConfig | Configuration structure for ArchXT_MiscRegCtrl |
| CArchXT_NVMConfig | Configuration structure for ArchXT_NVM |
| CArchXT_PortConfig | Configuration structure for ArchXT_Port |
| CArchXT_PortMuxConfig | Configuration structure for ArchXT_PortMuxCtrl |
| CArchXT_RTCConfig | Configuration structure for ArchXT_RTC |
| CArchXT_SPIConfig | Configuration structure for ArchXT_SPI |
| CArchXT_TimerAConfig | Configuration structure for ArchXT_TimerA |
| CArchXT_TimerBConfig | Configuration structure for ArchXT_TimerB |
| CArchXT_TWIConfig | Configuration structure for ArchXT_TWI |
| CArchXT_USARTConfig | Configuration structure for ArchXT_USART |
| CArchXT_VREFConfig | Configuration structure for ArchXT_VREF |
| CArchXT_WDTConfig | Configuration structure for ArchXT_WDT |
| ►Cbase_reg_config_t | |
| CACP::channel_config_t | |
| CADC::channel_config_t | |
| CArchAVR_ACPConfig::mux_config_t | |
| CArchAVR_ADCConfig::reference_config_t | |
| CArchAVR_ADCConfig::trigger_config_t | |
| CArchAVR_FusesConfig::bootsize_config_t | |
| CArchAVR_TimerConfig::COM_config_t | Configuration structure for one COM setting |
| CArchAVR_TimerConfig::OC_config_t | Configuration structure for one compare channel |
| CArchAVR_TimerConfig::clock_config_t | Configuration structure for clock source/prescaler options |
| CArchAVR_TimerConfig::mode_config_t | Configuration structure for timer modes |
| CArchXT_ADCConfig::reference_config_t | |
| CArchXT_PortMuxConfig::mux_map_entry_t | Structure defining the mux ID corresponding to a register field value |
| CArchXT_RTCConfig::clksel_config_t | Configuration structure for each supported source clock |
| CArchXT_VREFConfig::reference_config_t | Structure defining the source of a voltage reference |
| CSleepConfig::mode_config_t | Configuration structure for each supported sleep mode |
| Cbitmask_t | Bit mask structure for bitwise operations on 8-bits registers |
| Cbitspec_t | Bit spec structure. Represent a field in a I/O register. It works the same as bitmask_t except used bits must be consecutive |
| CFirmware::block_view_t | |
| Cbreakpoint_t | Breakpoint structure |
| CArchXT_VREFConfig::channel_t | |
| CPin::controls_t | |
| ►CCore | AVR core generic model |
| CArchAVR_Core | Implementation of a CPU core for AVR series The main addition is to handle the address mapping in data space |
| CArchXT_Core | Implementation of a core model for Mega0/Mega1 series |
| ►CCoreConfiguration | |
| CArchAVR_CoreConfig | |
| CArchXT_CoreConfig | Configuration structure for ArchXT_Core |
| Cctlreq_data_t | |
| CCycleManager | |
| ►CCycleTimer | |
| CBoundFunctionCycleTimer< ArchAVR_IntCtrl > | |
| CBoundFunctionCycleTimer< ArchAVR_WDT > | |
| CBoundFunctionCycleTimer< ArchXT_NVM > | |
| CBoundFunctionCycleTimer< ArchXT_WDT > | |
| CBoundFunctionCycleTimer< UART::USART > | |
| CArchAVR_NVM::EE_Timer | |
| CArchAVR_NVM::SPM_Timer | |
| CArchAVR_SPI::_Controller | |
| CArchXT_SPI::_Controller | |
| CBoundFunctionCycleTimer< C > | |
| CPrescaledTimer | Generic model of a Timer with prescaling |
| ►CTWI::Client | Base abstract definition for a TWI client. This class implements the basic state machine to interface a TWI bus as a client. It is design to be controlled by a upper layer object (a controller). The interface notifies the controller of bus events (start, address, etc) via the signals and the controller shall use the API of this class to react accordingly |
| CArchAVR_TWI::_Client | |
| CArchXT_TWI::_Client | |
| ►CTWI::Host | Base abstract definition for a TWI host. This class implements the basic state machine to interface a TWI bus as a host. It is design to be controlled by a upper layer object (a controller). The interface notifies the controller of bus events (start, address, etc) via the signals and the controller shall use the API of this class to react accordingly |
| CArchAVR_TWI::_Host | |
| CArchXT_TWI::_Host | |
| ►CDevice | Basic AVR device model |
| CArchAVR_Device | Implementation of a MCU for AVR series |
| CArchXT_Device | Implementation of a device model for Mega0/Mega1 series |
| CDeviceConfiguration | |
| CDeviceDebugProbe | |
| CPinManager::drv_entry_t | |
| CDummyController::dummy_register_t | |
| ►CSPI::EndPoint | An endpoint connected to a SPI bus. Represents a device connected to a SPI bus model and acting as a host or client. This is primarily intended to help simulate peripherals connected to the MCU model. Note that this class only implements the logic require to shift bytes across the SPI bus in all modes or bit orders |
| CArchAVR_SPI::_Controller | |
| CArchXT_SPI::_Controller | |
| ►CTWI::EndPoint | An endpoint connected to a TWI bus. Represents a device connected to a TWI bus model and implements the basic level logic common to a host and a client |
| CTWI::Client | Base abstract definition for a TWI client. This class implements the basic state machine to interface a TWI bus as a client. It is design to be controlled by a upper layer object (a controller). The interface notifies the controller of bus events (start, address, etc) via the signals and the controller shall use the API of this class to react accordingly |
| CTWI::Host | Base abstract definition for a TWI host. This class implements the basic state machine to interface a TWI bus as a host. It is design to be controlled by a upper layer object (a controller). The interface notifies the controller of bus events (start, address, etc) via the signals and the controller shall use the API of this class to react accordingly |
| CArchAVR_ExtIntConfig::ext_int_t | |
| CFirmware | |
| ►CInterruptHandler | Abstract interface to a interrupt controller |
| ►CAbstractInterruptFlag | Abstract interrupt flag |
| CArchXT_Port::_InterruptHandler | |
| CArchXT_SPI::_InterruptHandler | |
| CInterruptFlag | Generic helper to manage a typical Interrupt Flag/Enable in a I/O register |
| CArchAVR_ExtInt | Implementation of a model for a External Interrupts peripheral for AVR series |
| CArchAVR_NVM | Implementation of a NVM controller for AVR series |
| CArchAVR_WDT | Implementation of a Watchdog Timer for AVR series |
| Cioreg_write_t | |
| ►CIORegHandler | |
| CIORegDispatcher | |
| CInterruptFlag | Generic helper to manage a typical Interrupt Flag/Enable in a I/O register |
| ►CPeripheral | Abstract class defining a framework for MCU peripherals |
| CArchAVR_ACP | Implementation of an Analog Comparator for AVR series |
| CArchAVR_ADC | Implementation of an ADC for AVR series |
| CArchAVR_ExtInt | Implementation of a model for a External Interrupts peripheral for AVR series |
| CArchAVR_Fuses | Implementation of a fuse NVM peripheral for AVR series |
| CArchAVR_MiscRegCtrl | Implementation of a misc controller for AVR series |
| CArchAVR_NVM | Implementation of a NVM controller for AVR series |
| CArchAVR_ResetCtrl | Implementation of a Reset controller for AVR core series |
| CArchAVR_SPI | Implementation of a SPI interface for AVR series Features: |
| CArchAVR_TWI | Implementation of a TWI model for the AVR series |
| CArchAVR_Timer | Timer/Counter model for AVR series |
| CArchAVR_USART | Implementation of a USART interface for AVR series |
| CArchAVR_USI | Implementation of a Universal Serial Interface for AVR series |
| CArchAVR_WDT | Implementation of a Watchdog Timer for AVR series |
| CArchXT_ACP | Implementation of an Analog Comparator for XT core series |
| CArchXT_ADC | Implementation of an ADC for XT series |
| CArchXT_Fuses | Implementation of a fuse NVM peripheral for XT series |
| CArchXT_MiscRegCtrl | Implementation of a controller for misc registers for XT core series |
| CArchXT_NVM | Implementation of a NVM controller for Mega0/Mega1 series |
| CArchXT_PortMuxCtrl | Implementation of a generic portmux controller for XT core series |
| CArchXT_RTC | Implementation of a RTC controller for XT core series |
| CArchXT_ResetCtrl | Implementation of a Reset controller for XT core series |
| CArchXT_SPI | Implementation of a Serial Peripheral Interface controller for the XT core series |
| CArchXT_TWI | Implementation of a Two Wire Interface for XT core series |
| CArchXT_TimerA | Implementation of a Timer/Counter type A for the XT core series |
| CArchXT_TimerB | Implementation of a Timer/Counter type B for the XT core series |
| CArchXT_USART | Implementation of a USART interface for XT core series |
| CArchXT_USERROW | Implementation of a User Row peripheral for XT core series |
| CArchXT_WDT | Implementation of a Watchdog Timer for XT core series |
| CDummyController | Generic dummy peripheral |
| ►CInterruptController | Generic interrupt controller |
| CArchAVR_IntCtrl | Implementation of a interrupt controller for AVR series |
| CArchXT_IntCtrl | Implementation of a Interrupt Controller for XT core series |
| ►CPort | Generic model for a GPIO port controller |
| CArchAVR_Port | Implementation of a GPIO port controller for AVR series |
| CArchXT_Port | Implementation of a GPIO port controller for XT core series, based on the generic Port class |
| CSleepController | Generic sleep mode controller |
| ►CVREF | Generic model for managing VREF for analog peripherals (ADC, analog comparator) |
| CArchAVR_VREF | Implementation of a Voltage Reference controller for AVR series |
| CArchXT_VREF | Implementation of a voltage reference controller for XT core series |
| CIORegister | |
| CInterruptController::IRQ_t | |
| CLogger | |
| CLogHandler | |
| CLogWriter | |
| CMemorySectionManager | Memory section management |
| CArchXT_PortMuxConfig::mux_config_t | |
| CNonVolatileMemory | Non-volatile memory model |
| CNVM_request_t | Structure used for AVR_CTLREQ_NVM_REQUEST requests |
| CArchAVR_Timer::OutputCompareChannel | |
| CArchAVR_ExtIntConfig::pc_int_t | |
| CPinManager::pin_entry_t | |
| ►CPinDriver | MCU pin driver |
| CArchAVR_SPI::_PinDriver | |
| CArchAVR_TWI::_PinDriver | |
| CArchAVR_USART::_PinDriver | |
| CArchAVR_USI::_PinDriver | |
| CArchXT_SPI::_PinDriver | |
| CArchXT_TWI::_PinDriver | |
| CArchXT_TimerA::_PinDriver | |
| CArchXT_TimerB::_PinDriver | |
| CArchXT_USART::_PinDriver | |
| CPinManager | MCU pin manager |
| Creg_addr_t | Representation of a I/O register address, with validity state |
| Cregbit_compound_t | |
| Cregbit_t | Represents a field in a I/O register with address |
| Cregmask_t | Address + bit mask structure |
| ►CSignal | Signalling framework class |
| CDataSignal | |
| Csignal_data_t | |
| ►CSignalHook | |
| CBoundFunctionSignalHook< ArchAVR_ACP > | |
| CBoundFunctionSignalHook< ArchAVR_ADC > | |
| CBoundFunctionSignalHook< ArchAVR_ExtInt > | |
| CBoundFunctionSignalHook< ArchAVR_IntCtrl > | |
| CBoundFunctionSignalHook< ArchAVR_TWI > | |
| CBoundFunctionSignalHook< ArchAVR_Timer > | |
| CBoundFunctionSignalHook< ArchAVR_USART > | |
| CBoundFunctionSignalHook< ArchAVR_USI > | |
| CBoundFunctionSignalHook< ArchXT_ACP > | |
| CBoundFunctionSignalHook< ArchXT_ADC > | |
| CBoundFunctionSignalHook< ArchXT_NVM > | |
| CBoundFunctionSignalHook< ArchXT_TWI > | |
| CBoundFunctionSignalHook< ArchXT_TimerA > | |
| CBoundFunctionSignalHook< ArchXT_TimerB > | |
| CBoundFunctionSignalHook< ArchXT_USART > | |
| CBoundFunctionSignalHook< Port > | |
| CBoundFunctionSignalHook< TimerCounter > | |
| CArchXT_RTC::TimerHook | |
| CBoundFunctionSignalHook< C > | |
| CDataSignalMux | |
| CSleepController | Generic sleep mode controller |
| Csim_id_t | Representation of a ID internally represented as a 64-bits integer but can be initialised with a string |
| CSleepConfig | Configuration structure for a generic sleep mode controller |
| CWire::state_t | |
| CFirmware::Symbol | |
| CTimerCounter | Generic model of a Counter |
| CCycleManager::TimerSlot | |
| ►CUART::USART | Generic model defining an universal synchronous/asynchronous serial interface a.k.a. USART |
| CArchAVR_USART::_Controller | |
| CArchXT_USART::_Controller | |
| Cvardata_t | |
| CArchXT_IntCtrl::vect_info_t | |
| CArchAVR_TimerConfig::vector_config_t | Configuration structure for one interrupt vector |
| ►CWire | General Purpose wire model |
| CPin | MCU pin model |
1.9.8